Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21325 Discussions

probleme when fitting DDR2 DQ : critical warning

Altera_Forum
Honored Contributor II
‎09-02-2011 02:05 PM
1,099 Views

Hi, 

 

I am trying to map a cyclone IV with 3 DDR2 : 

- fpga = EP4CE30 F484 

- DDR2 micron 512mb x16 (MT47H32M16HR-25EG) 

 

I both try manual and automatic assignment but I always have this critical warning : 

 

Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/O 

 

What does properly means ? do I have to remove this wrning and how ? 

 

thanks.
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.