problems with uart on a tri-state bus

Altera_Forum · ‎09-30-2009

hi everyone! thanks in advance if someone could help me or tell me some ideas to get my project works. i dont know what is the problem, maybe i'm completely wrong...

im developing a new design consist on a nios II processor that access (send and write) some data to a external 16750 uart.

Because of the uart is a external peripheral, i created a tri-state bus on the sopc builder and a new component with a slave tri-state template and then conected through the bus.

i generate the system and everything is ok. Then i connect the uart to the nios processor and compile the quartus project without any problem.

finally i write a c program nios ide to test my project, but i cant access the uart... i dont know whats going wrong...:confused:

Any idea?

PS: sorry for m english, its not my native language...

Altera_Forum · ‎09-30-2009

Check the polarity of your control signals. RST, RD and WR are active low, but CS is active high in your SOPC project.

Altera_Forum · ‎09-30-2009

--- Quote Start ---

Check the polarity of your control signals. RST, RD and WR are active low, but CS is active high in your SOPC project.

--- Quote End ---

i read the datasheet of the 16750 uart and i got the conclusion that CS, RD and WR are all active low, but reading the vhdl code of the core (i downloaded the uart from opencores.org) i think RD, WR and CS are active high... now i'm a little bit confused...

here is the .vhdl file for the uart... if you could check it out to confirm me the polarity of the signals it will be really helpful to me! thanks.

Altera_Forum · ‎09-30-2009

Yes, all the control signals are active high in this VHDL file.

Altera_Forum · ‎09-30-2009

i changed the polarity of the signals... but now i dont know how to access to the uart from the nios ide... :/

Altera_Forum · ‎10-01-2009

You will have to write a driver for the UART.

You can use the IORD and IOWR macros to access the registers inside the component.

Altera_Forum · ‎10-01-2009

one question... on the sopc builder i have the configure in the tristate bus what signals are going to be shared with the custom component... it's enough with data_bus and address_bus or it's going to be necesary to share cs, wr and rd signals too??

Altera_Forum · ‎10-02-2009

If you have only one component on the tristate bus, these options won't change anything. They just select which signals will be shared between several external components connected to the tristate bus.