process error ... sensitivity list or wait statement?

[Altera_Forum]

HI. I am starter in vhdl. 

I wrote the source , but it doesn't work... Quartus said that process statement must contain either sensitivity list or wait statement:mad:.. but I can't understant what it means.. How can i solve this problem?.. If anybody is possible,, show me the right source with below source. Thanks!       LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ex is   PORT(  c : IN std_logic;  d : IN std_logic_vector(3 downto 0);  x : OUT std_logic_vector(3 downto 0));   end ex;   ARCHITECTURE arc of ex is BEGIN  PROCESS  BEGIN  FOR i IN 3 downto 0 loop  x(i)<= d(i) XOR c;  END loop;  END PROCESS; END arc;

[Altera_Forum]

Quartus is simply requiring a sensitivity list in this case. Review your VHDL text book about the purpose of sensitivity lists. 

 In a combinational process, the sensitivity list should contain all input signals. process(d,c)

[Altera_Forum]

Thanks. It's really helpful .

[Altera_Forum]

Hello, 

 i've got a process with lots of signals in the sensitivity list, but it doesn't activate, in order to enter allways i removed the sensitivity list, and it required me the wait until, that i didn't manage it to work since it tells me to use a time clause and then (as soon as I created a time one) a boolean one, so i decided to post my code after the begin of the architecture without any process, and does not work anyway, how do you do for creating a permanent rolling process (just for debug)?

[Altera_Forum]

Hiow about making a new post. I dont think this question is related to the existing post. Or you could at least post some of the problem code .

[Altera_Forum]

Yes, sorry, it was a similar post, the fact is i've found the error, and i've posted the answer in other forum.