programming successful but no function of CPLD

[Niko3]

Hi, I am quite new with CPLD design and hope to get help here.

For test purposes and learning I made a simple schematic with an external clock of 1 kHz, a 4bit counter (74161) and a BCD to 7 segment decoder (7448). All 4 outputs from counter and 7 outputs from decoder are available on pins of the CPLD.

I programmed a MAX300 EPM3064ATC44 on a self made board with a USB Blaster Rev. c. Quartus II programmer reported 100% successful programming and verification. But the counter outputs don't look like binary counting. They are totally confused.

I also programmed the same schematic to a MAXII EPM240T100 on a test board from ebay. Again programming was successful but counter outputs are confused.

The USB Blaster is a clone from ebay. It contains a STM32FEB but no output driver for level conversion. Both boards, my self made one and the board from ebay, are powered with 3.3 V and also VCC_IO for both chips is 3.3 V. Therefore level conversion is not necessary.

The board from ebay was delivered programmed with a blinking example. Therefore the chip should be ok.

What could have happened that after successful programming the chips don't work as expected?

A picture of the ebay board and USB Blaster ist attached.

[FvM]

Hi,
I suspect your code in the first place.

[Niko3]

I didn't write code. I used the block editor to design the schematic, see attachment (for EPM240).

I also made a simulation which showed correct waveforms.

[FvM]

Hi,
how do you observe the counter output? What's the 1 kHz external clock source, sure it's suited as CPLD clock?

[Niko3]

I use a DSO/state analyzer. It has a 5V  1 kHz clock output. The 5V output is scaled down to 2.8V with a serial resistor and a zener diode.

Five channels of the state analyzer show the clock input and the 4 counter outputs which are connected to pins of the CPLD.

[FvM · Accepted solution]

Hi,
which series resistor value? Clock edge may be too slow and cause multiple transitions. As you say it's a self designed board, insufficient power supply bypassing and ground bounce can cause irregular CPLD behaviour.

[Niko3]

Thank you FvM for your tips.

It really was a too slow clock slope. After many tests with varying conditions I had a look on the clock slope with high time resolution, see the attachment. The yellow track is the rising edge of original 1 kHz clock and the red one is after an inverter. With the improved slope my circuit works fine.

[NurAiman_M_Intel]

Hi,

May I know from where did you purchase the MAX3000? Is it from Intel authorized distributor?

MAX3000 were obsolete back in 2018.

Additionally, you can also refer to below page for MAX3000:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/max-3000-support.html

Regards,

Aiman

[NurAiman_M_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.