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question about AN 733 report and cyclone 10 GX development kit

Victor7
Beginner
97 Views

Hi, I'm currently working on applying the JESD204b IP core on cyclone 10 GX development kit and ads54j66evm from TI.  According to the AN 733: Altera JESD204B IP core and TI ADC12j4000 Hardware Checkout Report, the TI ADC12j400 works on the Stratix V Advanced Systems Development Kit. But the board reference manual for the Stratix V board shows that the FMC connector on the board is LPC and the schematic of the TI ADC12j4000 uses the K28, K29, K37, K38 as the sysref and the clock for the ADC. I wonder how this works when the HPC bank B (HB17 and HB06) is not activated and if this could work on the LPC+ FMC connector on the cyclone 10 GX development kit. Thanks a lot for your help. 

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3 Replies
ZiYing_Intel
Employee
79 Views

Hi,


Thanks for submitting the issue.

Allow me have some time to look into the issue and I will get back to you with findings.


Best regards,

Zi Ying


ZiYing_Intel
Employee
52 Views

Hi Victor7,

 

If you wish to use JESD204B IP on cyclone 10GX development kit, please do have a look on the pdf below, 

https://www.intel.com/content/www/us/en/docs/programmable/683298/21-3-19-2-0/fpga-ip-design-example-...

 

Best regards,

Zi Ying

 

ZiYing_Intel
Employee
22 Views

Hi,

 

Since long time no hear any feedback from you, I am now close this case.

 

Best regards,

Zi Ying

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