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Hey guys,
I want to know, if the Altera Cyclone 2 (EP2C5F256C8N) is able to handle an external 100 MHz trigger. I want to count the times the trigger is fired, and as far as I know it should be fired with a frequency of 100 MHz. I hope you can help me. My code in verilog for the counter is like follows:module cntr(
input trigger,
input rst,
output counter
);
reg counter_d, counter_q;
assign counter = counter_q
always @(counter_q) begin
counter_d = counter_q + 1'b1;
end
always @(posedge trigger) begin
if (rst) begin
counter_q <= 16'b0;
end else begin
counter_q <= counter_d;
end
end
end
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Cyclone II should be able to comfortably run a relatively simple counter, such as yours, at 100MHz. My concern would be what your 'trigger' looks like.
If you'd posted code with the word 'clock' instead of trigger I wouldn't have questioned it any further. You've written a reasonably sensible block of synchronous logic. Providing your 'trigger' signal looks much like a regular clock, the FPGA won't have a problem. However, if your trigger's mark/space ration is something unusual, but still generating around 100M rising edges per second, you may find iratic behaviour. Anything like this would result in the need to constrain it to operate at a higher trigger (clock) frequency. Cheers, Alex
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