"Safe" state machine

[Altera_Forum]

Hi,  

Attached herewith is the Altera safe_state example. I want to build my code around this kind of state machine (for robust design).  My question is why didn't you used "when others" in your example. What would happen if I'll still write it down in the end of the case statement? In general, are there any restrictions that I should know before I'm implementing the "Safe" form in all my designs (a reference document will do as well…)?  Is it o.k. that I'll add the one-hot to the safe statement*? Is it recommended?     * attribute syn_encoding : string; attribute syn_encoding of state_type : type is "safe, one-hot";    Thanks, Idan

[Altera_Forum]

Because in the code, all cases have already been covered, and the when others would be redundant.

[Altera_Forum]

An others case not representing existing states is meaningless, both in standard and safe encoded FSM. If I remember right, the empty others case has been required by previous VHDL versions. 

 one-hot will be the default encoding in most cases, thus it can be expected meaningless as well.  The only drawback of safe enconding is a slight increase in LE usage, you can try yourself.