"std_logic_vector" is used but not declared

Altera_Forum · ‎02-18-2012

I worked with the book "Embedded SoPC Design..." from Chu and I have problem with my first (!) VHDL source code I typed from the book. I suppose this is very basic question - sorry about that.

The error I get: "std_logic_vector" is used but not declared ... but I thought, that is done by the use statement ....

library ieee;
use ieee.std_logic_1164.all;
entity eq1 is
   port(
      i0, i1: in std_logic;
      eq: out std_logic
   );
end eq1;
architecture sop_arch of eq1 is
   signal p0, p1: std_logic;
begin
   -- sum of two product terms
   eq <= p0 or p1;
   -- product terms
   p0 <= (not i0) and (not i1);
   p1 <= i0 and i1;
end sop_arch;
entity eq2 is
   port(
      a, b: in std_logic_vector(1 downto 0);
      aeqb: out std_logic
   );
end eq2;
architecture struc_arch of eq2 is
   signal e0, e1: std_logic;
begin
   -- instantiate two 1-bit comparators
   eq_bit0_unit: entity work.eq1(sop_arch)
      port map(i0=>a(0), i1=>b(0), eq=>e0);
   eq_bit1_unit: entity work.eq1(sop_arch)
      port map(i0=>a(1), i1=>b(1), eq=>e1);
   -- a and b are equal if individual bits are equal
   aeqb <= e0 and e1;
end struc_arch;

Altera_Forum · ‎02-18-2012

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The error I get: "std_logic_vector" is used but not declared ... but I thought, that is done by the use statement ....

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Your code has essentially two components in it. If you have multiple entities in a file, then you need the use statement above every entity declaration.

Cheers,

Dave

Altera_Forum · ‎02-18-2012

Thanks, that was it !

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Your code has essentially two components in it. If you have multiple entities in a file, then you need the use statement above every entity declaration.

Cheers,

Dave

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