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HBran2
Beginner
233 Views

removal VCXO, Avalon-MM addresses

stp_results.gifHi,

 

I try to remove VCXO module from my project and to use re-clock module as described here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an746.pdf

As you can see in the attached stp screenshot the PLL's locked signal fall, and TX side died.

I tried to analyze the Avalon M-M signals, but didn't find the relevant addresses description (12D, 12E, 12F and 130) , can you assist?

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1 Reply
JonWay_C_Intel
Employee
39 Views

Hi,

 

Could you please confirm if the reference clock of the

TX PLL is correct? As per the user guide, it is required to running @ 100MHZ

from oscillator.

 

Besides, you can refer to the following document to

generate the example example without VCXO from the IP GUI by using the newer

version of Quartus and see if encounter the same problem.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-sdi-ii-de.pdf

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