I try to remove VCXO module from my project and to use re-clock module as described here:
As you can see in the attached stp screenshot the PLL's locked signal fall, and TX side died.
I tried to analyze the Avalon M-M signals, but didn't find the relevant addresses description (12D, 12E, 12F and 130) , can you assist?
Could you please confirm if the reference clock of the
TX PLL is correct? As per the user guide, it is required to running @ 100MHZ
Besides, you can refer to the following document to
generate the example example without VCXO from the IP GUI by using the newer
version of Quartus and see if encounter the same problem.