rx simplex of transceiver reset problem

[lambert_yu]

Hi all,

   env : one rx simplex transceiver channel on one bank; one tx simplex transceiver channel on another bank;

   data pattern : prbs20

    fpga  & quartus version: 10ax115n2f45i2sg/ quartus standard 18.0

    Aim: force tx to transmite prbs20, and rx to receiver and decode this prbs pattern; during this procedure, I will test the time of the cdr lock to data .

    Problem:

     case 1:

           operation :

              a. every time, I will reset tx IP and make it to re-transmit the pattern;

              b. and for rx, before tx reset, I will force rx to lock to ref and do rx's digital reset and after tx transmits the pattern about 1us, I will force rx to lock to data and after about 4us, I will deassert rx's digital reset.

              c. result: I found that, rx prbs checker can not lock again. And I will do another lock to data -> lock to ref -> locktodata, rx prbs checker will lock again. (But for this method, I could not get one sure cdr lock time just because the rx prbs checker will not lock at the previous operation.

     case 2:     

       operation :

              a. every time, I will reset tx IP and make it to re-transmit the pattern;

              b. and for rx, before tx reset, I will force rx to lock to ref and do rx's digital reset and after tx transmits the pattern about 700us, I will force rx to lock to data and after about 4us, I will deassert rx's digital reset.

              c. result: I found that, rx prbs checker can lock again frequently. And I will not do another lock to data -> lock to ref -> locktodata, rx prbs checker will lock again. But the value of 700us is too large. And I found that gradually decrease this value, the frequency of lock will change to samll.

      case 3:

             operation:

                a. every time, I will not reset tx IP and tx will continue to transmit prbs pattern;

                b. only force rx to do  lock to data -> lock to ref -> locktodata and do rx digital reset when there's switch lock to ref to lock to data.

                c. rx prbs checker could lock everytime. (but for this case,  if I set small tLTD (about 0.8us), rx prbs checker will lock. this result is different to the minimum value (4us)). So I could not make sure this value is okay.

       Compared to case 1 and case 2, I want to know , for this same link, I reset tx IP every time, if I need to reset RX IP completely (that means I will not only to do lock to data -> lock to ref -> lock to data and rx digital reset, and I need to do rx digital reset) ? For case 3, I want to know if I donot reset TX, that means everything will be okay for rx pma?

       Could someone give me some advice?

[Kshitij_Intel · Accepted solution]

Hi,

Please assert the rx_analog_reset input to the reset controller that resets the RX CDR and RX PMA blocks of the PHY and that puts CDR in lock to ref clock then locked to data mode and then release the analog reset.

Thank you

Kshitij Goel

[lambert_yu]

Hi K**bleep**ij,

    Thanks for your answer, I have do the things like you said, and this method is okay.

Brs,

Lambert