sampled signal on falling or risins edge?

[Altera_Forum]

Hello, 

  I have a beginner question. With the code below   The signal in_width_pulse_n is wide of one period (clk_speed)  My question is on signal old1_width_pulse_n I must be sampled it on falling or rinsing edge.   Thank for you adice!  process(Rst, Clk_speed) begin if Rst = '0' then old1_width_pulse_n <= '1'; else  if Clk_speed = '1' and Clk_speed 'event  then  old1_width_pulse_n <= in_width_pulse_n;  end if; end if; end process;  process(Rst, Clk_speed) begin if Rst = '0' then old_width_pulse_n <= '1'; else  if Clk_speed = '1' and Clk_speed 'event  then  old_width_pulse_n <= old1_width_pulse_n;  end if; end if; end process;

[Altera_Forum]

The safer solution is to leave it sampled on the rising edge.  

But, if you don't have timing problems or signal ringing, the signal is available also on the falling edge (it is generated on the previous rising edge) so you may decide to go quicker and sample the signal on the falling edge.

[Altera_Forum]

Hello,  

 Thank for you answer. You can see these signal on attach file.  I don’t have problem on the design speed.  But though it was not sure sampled signal on rising edge if  it is generated on the previous rising edge. I ‘m anxious for metastability  problem: sampled signal when it change.    What do you think about that moreover if I test my fpga in incubator with a wide temperature range!

[Altera_Forum]

This is a common point of confusion for beginning logic designers. The questions at hand are not what edge to use for data sampling but instead are you meeting timing requirements. Every flip-flop has a setup and hold requirement. How long before the latching clock edge and how long after the clock edge must the data be present at the input of the flip-flop. 

 It is not typical in most designs to use both clock edges. The times for using both edges is when the behavior is an inherent part of the design itself (such as DDR interfaces).  Use the rising clock edge for both signals. The timing analyzer and fitter have the responsibility of determining whether or not the setup and hold times are being met. You can specify your temperature range in the project settings within Quartus II and the timing analyzer will take those settings into account.  Jake

[Altera_Forum]

Ok if I summarize. I can just use rising edge as long as the timing analyzer is ok. 

Except for communicate with external component.    But I though use alternative falling rising edge for a safer marging.:p

[Altera_Forum]

No the same rules apply when interfacing to an external component. The component has a setup and hold requirement on it's inputs. You must use these values in addition to your board trace delays to create timing constraints for your project. I have actually never used a falling clock edge to drive data out to an external component (except when creating DDR interfaces). There are occasions where it is appropriate. Those occasions are when all of the timing factors indicate a falling edge will give the best timing performance. 

 By using both edges for logic, you may actually be taking away from the timing margin. Essentially you are giving the fitter a tighter timing requirement that it has to work in. Yes you've made life easier for the fitter when it comes to meeting the hold requirement but you've made it twice as bad for setup. Here is the rule: always do everything on the same clock edge until you come across a very good reason not to. By that time you will have enough experience to know the difference.  Jake

[Altera_Forum]

I can add that use the falling rising not make your margin safer, but force your design to go twice faster. It's as if you use a clock of double frequency and on a rising edge clock you generate the data and on the following one you acquire it. 

 I really suggest you to not change the sampling edge and let the compiler do its work.

[Altera_Forum]

OK thank for you advice:)