set fault path P&R FPGA

[Altera_Forum]

whether the tcl script command 'set fault path' has an influence on the P&R or not ? If I set the fault path from node A to B, the timequest will not report the timing violation from node A to B, but I don't know whether it will influence the P&R from node A to B , further influence the P&R of the whole design.

[Altera_Forum]

set_false_path is used by the fitter, so it will allow that path to be spread out in order to help timing elsewhere. (Timing is the most important driver of the placer, but routability is second, so it's not uncommon for the fitter to put stuff close together that is physically connected anyway, since that improves routability.)