set_max_delay value in TimeQuest

[Altera_Forum]

Hi 

I should constaraint "set_max_delay -from reg_A to reg_B". In my case , My circuit run 200MHz(refer to wave picutre). I estimated register to register max delay value was 5.0ns . but TimeQuest said Data required 5.471 ns without any constraint.  Can TimeQuest latch delay_data after edge? and Why can it do like that?

[Altera_Forum]

TimeQuest is a timing analyser. It estimates a.o. the delays from register outputs to register inputs through your combinatorial logic. 

The message is indicating that your circuit is (probably) a little too slow (0.47 nsec too late).  So you should optimize the combinatorial logic in your circuit, reduce the depth of the combinatorial logic or add pipeline registers in between.

[Altera_Forum]

Dear sanmao 

 >So you should optimize the combinatorial logic in your circuit,  >reduce the depth of the combinatorial logic or add pipeline registers in between.  I thought I can constraint "set_max_delay -from reg_A to reg_B 5.40ns". is it OK? Becouse TimeQuest required 5.741ns in this path. It means, Can reg_b latch after Latch_edge in this pass ?