Hello!
I am using the avalon_st_clock_crosser IP in my Design which has a net_delay constraint of 2ns.
This is defined in the .../ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser folder.
Unfortunately this constraint can't be met in all cases by some few ten pico seconds, which is not really a problem itself.
I would like to modify the existing constrain (within my design) to get rid of the violation messages.
Other timing exceptions like set_max_delay or set_max_skew have a precedence that the last assignments overwrite earlier assignments.
"set_net_delay" seems to behave different.
set_net_delay -from X -to Y 2.001
set_net_delay -from X -to Y 2.002
set_net_delay -from X -to Y 2.003
.. results in having three additional timing violations instead of having only the one with the last setting.
Some (partially ugly) workarounds i thought of:
- changing the IP in the intel component folder
- copying the IP to my Project folder, change the IP there,
- disable automatic test of net delay violations and live with the violations with the risk of overlook some real violation, additional effort in manual verification
Is there a way to overwrite set_net_delay constraints that i am missing?
Thanks
Dirk
