simulation result of "case" is one clk delayed?

Altera_Forum · ‎07-15-2011

totally, in the module "vnp" there are 256(parameter N=256) "cnt"s to deal with.

every "cnt" should go through a "Cycle".

One Cycle contains 3 steps. So the value of "Cycle" goes from 2'b00 to 2'b10 then retun 2'b00 like 00 01 10 00 01 10 00 01........ as the cnt grows 0 1 2 3......

that is


......
Cycle=0;
......
case(Cycle)
 2'b00:
  ......
  Cycle<=Cycle+1;
 2'b01:
  ......
  Cycle<=Cycle+1;
 2'b10:
  ......
  Cycle<=0;
  cnt<=cnt+1;
endcase

following is the detailed code


 always@(posedge Clk)
  if(CNP_ON||!CE)begin
   flag<=1;
   Cycle<=0;
   cnt<=0;
   calc_a<=0;
   calc_b<=0;
   Mess_Buff_a<=0;
   Mess_Buff_a<=0;
   Mess_Buff_a<=0;
   Mess_Buff_b<=0;
   Mess_Buff_b<=0;
   Mess_Buff_b<=0;
   end
  else
   if(cnt==0&&flag==1)begin  
    cnt<=0;     
    flag<=0;    
    end
   else
    if(cnt==(N+1))begin
     cnt<=0;//reset cnt
     flag<=1;//reset flag
     end
    else
     case(Cycle)
      2'b00:begin
       if(!cnt)begin
        calc_a<={Mess_Din,Mess_Din,Mess_Din};
        Mess_Buff_a<=Mess_Din;
        end
       else begin
        calc_b<={Mess_Din,Mess_Din,Mess_Din};
        Mess_Buff_b<=Mess_Din;
        end
       Cycle<=Cycle+1;
        end
      2'b01:begin    //add SrcMem_Din in the second step
       if(!cnt)begin
        calc_a<=calc_a+{Mess_Din,Mess_Din,Mess_Din}
        +{SrcMem_Din,SrcMem_Din,SrcMem_Din};
        Mess_Buff_a<=Mess_Din;
        end
       else begin
        calc_b<=calc_b+{Mess_Din,Mess_Din,Mess_Din}
        +{SrcMem_Din,SrcMem_Din,SrcMem_Din};
        Mess_Buff_b<=Mess_Din;
        end
       Cycle<=Cycle+1;
        end
      2'b10:begin
       if(!cnt)begin
        calc_a<=calc_a+{Mess_Din,Mess_Din,Mess_Din};
        Mess_Buff_a<=Mess_Din;
        calc_b<=0;
        end
       else begin
        calc_b<=calc_b+{Mess_Din,Mess_Din,Mess_Din};
        Mess_Buff_b<=Mess_Din;
        calc_a<=0;
        end
       Cycle<=0;
       cnt<=cnt+1;
        end
      endcase

in the simulation wave (in the attachment)

at the red line

cnt==0 flag==0 Cycle==0

so 2'b00 in case(Cycle) begin


       if(!cnt)begin
        calc_a<={Mess_Din,Mess_Din,Mess_Din};
        Mess_Buff_a<=Mess_Din;
        end
       else begin
        calc_b<={Mess_Din,Mess_Din,Mess_Din};
        Mess_Buff_b<=Mess_Din;
        end
       Cycle<=Cycle+1;

but the simulation wave has a delay of one clock

i have marked it out with yellow arrowhead

as you see Mess_Buff_a[0]<=Mess_Din should be run when Cycle==2'b00

but it happens at Cycle==2'b01

the waveform of Cycle and cnt are right

please explain

thank you

Altera_Forum · ‎07-15-2011

--- Quote Start ---

as you see Mess_Buff_a[0]<=Mess_Din should be run when Cycle==2'b00

but it happens at Cycle==2'b01

--- Quote End ---

It doesn't happen at Cycle == 1. Mess_Buff_a[0] is updated in the same clock cycle when Cycle is incremented from 0 to 1, as your code commands. This is how synchronous logic works.

Altera_Forum · ‎07-16-2011

--- Quote Start ---

It doesn't happen at Cycle == 1. Mess_Buff_a[0] is updated in the same clock cycle when Cycle is incremented from 0 to 1, as your code commands. This is how synchronous logic works.

--- Quote End ---

thank you very much.

I have misunderstanding the codes.

the waveforms are right.