simulator problem

[Altera_Forum]

Probably missing something basic here but I set up a simple simulation with 8 data lines going into 8 d flipflops, a megawizard, with a clock input and 8 data line outputs. I changed several of the input signals to go high using the waveform editing tool in the vector file but when I run the simulation none of the output lines go high, any ideas?

[Altera_Forum]

Got it to work, had a pin functioning as undefined clock so the flipflops were never clocked in the simulation.

[Altera_Forum]

I also have the same problem. I also got the same error. How do I correct it? How do I go about it? I am doing a project on vending machine controller. I am using decoders. And no matter what I do the inputs, I have the same answer for eveything. No changes at all. 

 Thanks in advance

[Altera_Forum]

are you using a clock? is it properly defined in the simulator?

[Altera_Forum]

I am completely new to Altera. So please be patient with me. How can do you define a clock? I do not think I have defined the clock.

[Altera_Forum]

I've never used the Altera simulator, but basically your clock signal needs to change regularly from 0 to 1 and the flip flops will only update their outputs on the rising edge of the clock. There is probably a button in the waveform creator that can automatically generate a signal that regularly switches from 0 to 1 for you.

[Altera_Forum]

Oh yes, I do do that. But no matter how much ever I change the the clock signal to high or low, I get the same result. In some case, it takes the previous output result and then never change despite changing the inputs.

[Altera_Forum]

could you show us a screenshot of your waveforms?

[Altera_Forum]

--- Quote Start ---  Oh yes, I do do that. But no matter how much ever I change the the clock signal to high or low, I get the same result. In some case, it takes the previous output result and then never change despite changing the inputs.  --- Quote End ---    Hi,  I assume your are using the standard setting of the simulator. This means your are running a simulation where the timing of your FPGA is taken into account. You have  also the choice to use a "functional" simulation which don't use the timing. With this simulation you can check whether your design is "logical" correct working or not. You can change the setting in the simualtor itself. There is a field "simulation mode", change the setting to "functional" and generate a netlist ( press the button nearby) and re-run your simulation.   Kind regards  GPK