std_logic_vector vs array

[Altera_Forum]

Here is my question.... 

 Are these two equivalent?  1.  signal sig_name : std_logic_vector(0 to 511)(7 downto 0);  2.  type sig_name_array is array 0 to 511 of std_logic_vector(7 downto 0);  signal sig_name : sig_name_array;  Thanks.

[Altera_Forum]

i've done a lot of VHDL and have never seen 1. being used. 

 Usually 2. but (511 downto 0) instead of 0 to 511?  generally  type type_name is array (range) of element_type;  Hope that helps

[Altera_Forum]

Thanks for the reply. 

 What I realy need is to be able to have an array in the port entity.  This is what I'd like:  entity x is generic( constant_1 : integer := 50); port ( in_port : in array(0 to constant_1 -1) of std_logic_vector(7 downto 0)); end x;  I know that "in_port : in array(0 to constant_1 -1) of std_logic_vector(7 downto 0) is not legal in VHDL, but it shows what I'd like to do. This needs to be done because x is called at an upper level file twice with different values of constant_1 passed in. I want to size in_port differently based on the instantiation on the upper level file while using the same code.  Currently, I have this:  entity x is port ( in_port : in in_port_array_type); end x;  Where in_port_array_type is defined in a package file. But this does not allow sizing in_port_array_type differently in different instantiations of x.  I suppose I could make in_port a std_logic_vector with a range of...  ((constant_1*8) -1 downto 0) and then map it into an array type defined in x, rather than a package file.  So, if there is any way to have an array in the port, that would be the best. If someone knows how or if this can be done, please let me know. If I have to just make it a large std_logic_vector and map that vector to an array defined in the code, then thats the way I'll go.

[Altera_Forum]

looking in some VHDL references I have, it does say that unconstrained arrays are not possible in entities.  

 So I think the method you suggest is the best option....get it into a 1-D format.  Alternatively, perhaps, put the array into a memory block??

[Altera_Forum]

gmpstr, 

Very interesting! I'm glad I checked this out as it leads into something I'm trying now. I looked this up in my copy of "The Designer's Guide To VHDL" 2nd Edition by Peter Ashenden. Now I thought I was taught that VHDL cannot handle multidimentional arrays, I remembered wrong! In the book on page 88 he goes into multidimensional arrays, for some reason he likes using the lesser used standard types in his examples but here's his example (he also assumes we're smart enough to put in the proper VHDL file format); *skip*  TYPE point IS ARRAY (1 TO 3) OF real;  TYPE matrix IS ARRAY (1 TO 3, 1 TO 3) OF real; *skip*  VARIABLE p,q : point;  VARIABLE transform : matrix; *skip*  For i IN 1 TO 3 LOOP  q(i) := 0.0;   For j IN 1 TO 3 LOOP  q(i) := q(i) + transform(i,j) * p(j);   END LOOP;  END LOOP;  Now for this he states that this is a design to handle a three dimensional array where 'p' and 'q' are the point variables for the matrix transform. I don't know if this will help but its what I've got.  I've been doing some more research and try this; Don't use STD_LOGIC_VECTOR, it is an unconstrained array. Declare your own array of STD_LOGIC (not _VECTOR) creating your own constrained array. Use STD_LOGIC as the example above uses REAL. Give it a shot.