stratix5 PLL minimum input clock speed

[Altera_Forum]

What is the minimum input clock speed for Stratix V device? I have a 10 MHz clock that I can input into the device. I want to use a PLL to multiply it up to 160 MHz for use in the core. Can Stratix V do it?

[Altera_Forum]

According to the megawizard, 5-800 MHz are valid input frequencies, and the 10 MHz source with 160 MHz output is valid. 

 I would still put it in a temp design and compile it first however, sometimes you get warnings that may not show up in the megawizard.  Pete