Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Honored Contributor I
745 Views

syncronize nco on different fpga

Hi,  

i've to generate two sinusoidal signals (about 70Hz) with two different altera ip nco implemented i 2 different fpga (CLK=50MHz and CLK_EN=25khz). The sinusoid is sampled @ 25khz. 

 

The problem is that those signals should have the same phases.  

 

There is available a sync signal for that 2 fpgas. This sync is a pulse with 100ms period and 10ns bit width. Eventually I can change the period.  

 

How could i use this sync signal in order to correct the phase of NCOs and maintain two output signals in phase coherence? 

 

Could you help me? Have you any idea to meet this issue? 

 

Thanks
0 Kudos
7 Replies
Highlighted
Honored Contributor I
3 Views

 

--- Quote Start ---  

Hi,  

i've to generate two sinusoidal signals (about 70Hz) with two different altera ip nco implemented i 2 different fpga (CLK=50MHz and CLK_EN=25khz). The sinusoid is sampled @ 25khz. 

 

The problem is that those signals should have the same phases.  

 

There is available a sync signal for that 2 fpgas. This sync is a pulse with 100ms period and 10ns bit width. Eventually I can change the period.  

 

How could i use this sync signal in order to correct the phase of NCOs and maintain two output signals in phase coherence? 

 

Could you help me? Have you any idea to meet this issue? 

 

Thanks 

--- Quote End ---  

 

 

use sync arrival to create logic for clock enable on NCO. And you need to account also for delays of two nco at point of check
0 Kudos
Highlighted
Honored Contributor I
3 Views

Could you explain me better your idea? 

Is it non feasable for you to correct the phase during normal working? 

Let me know.
0 Kudos
Highlighted
Honored Contributor I
3 Views

 

--- Quote Start ---  

Could you explain me better your idea? 

Is it non feasable for you to correct the phase during normal working? 

Let me know. 

--- Quote End ---  

 

 

An NCO has clock enable input. If it is enabled then it starts and works as long as it is enabled and will start from zero phase(by default). 

So if you have a sync pulse then wait for it in each fpga and assuming they arrive at NCO at same time then both NCOs can be enabled together from zero phase. All you need is convert that sync pulse to high signal starting once sync pulse arrives. Then the two outputs will go to DACs I assume and again delay issues may arise which you can measure and adjust digitally to within your available clock resolution. 

 

You can also allow both to run freely then correct phase if you get copy of one fpga output to the other but this is overkill. You may also have ways to align in the analogue side but that is not my territory. 

 

If your system is reliable you can also just measure the default delay and correct the phase in one fpga by offset if available on your nco or by starting one nco under control of clock enable.
0 Kudos
Highlighted
Honored Contributor I
3 Views

 

--- Quote Start ---  

So if you have a sync pulse then wait for it in each fpga and assuming they arrive at NCO at same time then both NCOs can be enabled together from zero phase. All you need is convert that sync pulse to high signal starting once sync pulse arrives. 

--- Quote End ---  

 

So i've to reset NCO at first pulse of sync and start to generate a clk-enable? How can i manage the problem of 2 different clock drift during time (50MHz 50PPM)? 

 

 

--- Quote Start ---  

Then the two outputs will go to DACs I assume and again delay issues may arise which you can measure and adjust digitally to within your available clock resolution. 

--- Quote End ---  

 

Actually the NCO output is compared with triangular wave and a pwm for inverter is generated.
0 Kudos
Highlighted
Honored Contributor I
3 Views

If you wish you can just use the pulse as reset and that may be enough as long as you want a simple design and anytime during running you may apply that reset if required. 

 

You still need your clock enable @ 25KHz as your clock rate is 50MHz. 

 

Now I expected the two clocks are from same source.If they are from different sources(unrelated) then you got some more work to do since phase and frequency drift will occur. 

One method is to create a sort of PLL as follows: 

 

one fpga(master) will need both clocks available. you run a counter on each clock that increments from zero on master clock and decrements on slave clock. Add them together. 

If clocks are tied up then the sum will stay. If they are not tied up the sum will give you error and its sense. 

 

You use that error to generate enable on master nco., based on modulo adder. for example you use 20 bit accumulator that increments/decrements by the error (will need some scaling). 

If the master counter is faster you slow it down and vice versa by generating enable at accumulator overflow. for 70Hz sinusoid this method should be fine.
0 Kudos
Highlighted
Honored Contributor I
3 Views

Unfortunately the system is composed by two different fpgas with 2 different clocks' sources because the fpgas are located on 2 independent boards. The sync pulses come from an external cpu (another board in the system). 

 

I'd like the idea of PLL but i don't know how to implement it.... 

The simplest way for me in order to avoid heavy changes on alredy written code is acting on NCO inputs.  

Have you any ideas? 

Thanks
0 Kudos
Highlighted
Honored Contributor I
3 Views

 

--- Quote Start ---  

Unfortunately the system is composed by two different fpgas with 2 different clocks' sources because the fpgas are located on 2 independent boards. The sync pulses come from an external cpu (another board in the system). 

 

I'd like the idea of PLL but i don't know how to implement it.... 

The simplest way for me in order to avoid heavy changes on alredy written code is acting on NCO inputs.  

Have you any ideas? 

Thanks 

--- Quote End ---  

 

 

For two untied clocks(clk1 & clk2) it is not doable in principle unless you have some signal from one clk to other clock domain.  

Your sync pulse must be 20ns (not 10ns) and may be it is generated in clk1 domain. In this case you might be able to apply your PLL to count time in between pulses (nominally 100ms) in clk2 domain.  

As I said you can then use an accumulator that adds up this counter value to generate an enable pulse that can be ANDed with you clock enable on NCO2. 

for example if it counted less then clk2 is slower so increase your enable rate on NCO2 and vice versa. keep NCO1 as it is. You will also need to cross clock domain carefully and a small dual clock fifo will help to read the sync pulse from clk1 domain into clk2 domain
0 Kudos