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timing constraint for clk using timer

XQSHEN
Novice
195 Views

I used timer to divide original system clk.

when doing timing constraint to create generated clock,  the source clock, should get_pin from original system_clk or direct from clk_timer register output? It seems clk_timer has 16 register, I don't know which one be used. And there are also some combination logic after clk_timer register.

 

always @(posedge clk or negedge reset_n) begin
if(reset_n == 1'b0)
       clk_timer <= 16'd0;
else if(spi_current_state == SPI_STATE_WRITE)
       clk_timer <= clk_timer + 16'd1;
else
       clk_timer <= 16'd0;
end

 


assign spi_inclk = (clk_timer[15:5] >= 16'd2 && clk_timer[15:5] <= (clk_limit[15:5] - 11'd2) && clk_timer[4:0] >= 5'd16);

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XQSHEN
Novice
193 Views

Addtional information: the system clk comes from PLL.

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