troubled in pll Reconfiguration in ep3c25q240c8

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

troubled in pll Reconfiguration in ep3c25q240c8

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i follow the steps in the 'Phase-Locked Loops Reconfiguration (ALTPLL_RECONFIG)Megafunction User Guide' .

I reconfigure the c0 counter using the ALTPLL_RECONFIG megafunction to vary the frequency of this counter by changing the c value.

but, after the signal 'scandone' asserted,the pll lose lock.

(i am using the chip ep3c25q240c8)

why, coud you help me?

i have upload my project.

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