two avalon buses in one FPGA tutorial?

[Altera_Forum]

Hi, 

 I know it is possible to have multiple avalon buses in one FPGA, but how can I do it? somebody know where I can found a tutorial?  Thanks,  Sam

[Altera_Forum]

What do you want to go exactly? If you just connect two separate masters to two separate slaves, then you will have two separate Avalon buses.

[Altera_Forum]

--- Quote Start ---  What do you want to go exactly? If you just connect two separate masters to two separate slaves, then you will have two separate Avalon buses.  --- Quote End ---   So 2 nios II proccesor and I have 2 Avalon buses?

[Altera_Forum]

Yes... or no. 

If you connect your two Nios II processors to the same memory, for example, they will share a common bus. If you connect them individually to two separate memories, then you'll have two buses.

[Altera_Forum]

So one nios II with the sdram and other nios II with de sram ? 

then I will have 2 busses?

[Altera_Forum]

At a guess the sram and sdram interfaces share pins. 

So eventually there will need to be an arbiter of some sort.

[Altera_Forum]

What I want is to use 1 nios II processor with 2 avalon busses. 

1 bus for the sram and other bus for the sdram.  is this possible?  if yes how?

[Altera_Forum]

AFAIK the SRAM and the SDRAM don't share any pins, but the SRAM and the CFI flash do, on the kits that have a parallel flash. 

If you use only one Nios CPU it has only one data master, so it will share it between the two memories anyway. Why exactly do you absolutely want 2 buses?

[Altera_Forum]

Also remember that the avalon 'bus' isn't like a normal cpu bus. 

It is 'slave arbitrated' - so there is an arbiter and mux in front of each slave that can be accessed by multiple masters. So two different masters can access two different slaves without there being any contention.

[Altera_Forum]

But how can I make 2 avalon busses? 

I am a beginner in this dont understand it so good

[Altera_Forum]

Perhaps you should explain what you are trying to achieve.

[Altera_Forum]

I want a separate communication with the sram

[Altera_Forum]

If you have two different Avalon masters (eg two different nios cpu) they can do bus cycles to different Avalon slaves at the same time. 

Arbitration only happens when two masters try to access the same slave at the same time.