Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21324 Discussions

unconstrained Path

Altera_Forum
Honored Contributor II
1,451 Views

Hi, 

 

 

After running the TimeQuest tool and clock constrain to 10MHz clock, I get all blue exact "unconstrained Path" (attached, marked in red,).  

 

 

What does it mean? Is something wrong with my code? (Fmax=15MHz, Fclock=10MHz). 

 

 

 

Thanks, 

 

 

Idan  

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
338 Views

It refers to inputs and outputs paths. Unless you add set_input_delay and set_output_delay then the tool wouldn't know about those paths. If you are designing an internal module (not final integration yet) then you can ignore these warnings until such time when you assign pins in the final stages in which case you need to know the external input/output devices timing parameters such as tCO,tSU,tH

0 Kudos
Reply