undesired sidebands on Cyclone IV E PLL output

[Altera_Forum]

I am using a PLL in a Cyclone IV E. I have a 20 MHz oscillator connected to a clock-input pin. I am trying to get 200 MHz as the output. For the design, I am using only an ALTPLL megafunction block with the clock input and c0 output. Most of the defaults are being used for the ALTPLL (except for the input and output frequency, which are 20 MHz and 200 MHz respectively). 

 When I look at the output on a spectrum analyzer, I see the 200 MHz signal, but I also see sidebands every 22 kHz. Ideally, I would like these sidebands to not exist on the output.   I have tried playing around with some of the PLL settings. I have noticed that setting the bandwidth to "high" causes the sidebands to decrease in amplitude. Setting it to "low" causes them to increase in amplitude.   Any ideas on causes for this? I have not dealt with these PLLs before, so any help would be appreciated!

[Altera_Forum]

Nevermind, problem solved. The issue was due to a faulty VCCA regulator that had 22 KHz oscillations on its output. 

 Lesson learned: a sloppy VCCA equals sloppy PLL outputs.

[Altera_Forum]

Glad that you solved your problem. But I also take it that you used a switcher for the 2.5V due to the 22kHz oscillations, and because of this an LDO is a good conservative design approach. Knowing the sensitivity of the PLL's is why I use LDO + LC filters, with large, medium tantalum caps and also a ceramic cap. Best, James

[Altera_Forum]

The VCCA regulator I am using actually is an LDO. Oscillations on its output were appearing due to a misinterpretation of its datasheet on my part (incorrect bypass and output cap values). The fact that it was an LDO unfortunately made it one of the last things I suspected.

[Altera_Forum]

That is a tough one to figure out, because that is out of the normal for the LDO. This is also another reason why I often debate on using a chip such as the Lattice power manager series of chips, and qualifying all the voltage rails before allowing connection downstream. This adds cost and complexity to the board, but the larger the $ of the FPGA, the more and more valuable such a protection scheme takes on value. -James

[Altera_Forum]

--- Quote Start ---  Glad that you solved your problem. But I also take it that you used a switcher for the 2.5V due to the 22kHz oscillations, and because of this an LDO is a good conservative design approach. Knowing the sensitivity of the PLL's is why I use LDO + LC filters, with large, medium tantalum caps and also a ceramic cap. Best, James  --- Quote End ---       This is the approach I have taken too, but be aware that for many LDO's the power supply rejection ratio (for noise) drops off massively with frequency so high frequency switcher noise can get through.   I had a good app note about this that recommended ferrite beads _around_ the output wires (I have used ferrites in line with varying values of caps). Unfortunately I can't find it right now.   Nial.

[Altera_Forum]

Ah, good old Jim Williams. Miss that guy. I can't post links, so just google  

 jim williams application note 101  Great article.

[Altera_Forum]

--- Quote Start ---  Ah, good old Jim Williams. Miss that guy. I can't post links, so just google    jim williams application note 101   Great article.  --- Quote End ---       The very App note I was talking about    http://cds.linear.com/docs/application%20note/an101f.pdf     Nial