Re: up/down counter

Altera_Forum · ‎01-23-2017

Hello,

can i get help for this program i am new to altera.

i need help making a program that has an up and down counter from 15-0 using pushbuttons and 2 seven 7-segments display

if its at 15 i press the decrement button once it should be 14

if its at 8 i press the increment button once it should be 9

your help is much appreciated.

Altera_Forum · ‎01-23-2017

and when the counter reaches 0 it will display .F

Altera_Forum · ‎01-23-2017

What have you written so far and what problems are you encountering?

Altera_Forum · ‎01-23-2017

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter is

port ( clk : in std_logic;

reset_bar : in std_logic;

q : out std_logic_vector (2 downto 0));

end counter;

architecture flow of counter is

signal count_sig : unsigned ( 2 downto 0);

begin

process ( clk, reset_bar)

begin

if (reset_bar ='0' ) then

count_sig <= "000";

elsif falling_edge (clk) then

count_sig <= count_sig +1;

end if;

end process;

q<= std_logic_vector (count_sig);

end flow;

i can only do a up counter but not both up and down and also how do i put up to 2 digits?

Altera_Forum · ‎01-23-2017

so depending on a signal you want it to either count up or down, what hardware do you expect?

as you want to change behaviour depending on a signal, use a mux, try to read about how to implement those in hardware.

Altera_Forum · ‎01-23-2017

Hello Malvin,

I wrote some code for the DE0_CV that generates a counter 0-255 based on 2 push buttons Key(0) and Key(1)

It sends the output to 2 7 seg display counters on a DE0-CV.

The quartus archive file is also included.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- interface with the pins of the fpga (imported file .csv for pin planner)
entity ent_main is
   port(
    -- clock on DE board:
    clock2_50: in std_logic;
    
    -- reset button:
    reset_n : in std_logic;
    
    -- push buttons:
    key: in std_logic_vector(3 downto 0);
    
    -- hex 7 seg displays:
    hex0: out std_logic_vector(6 downto 0);
    hex1: out std_logic_vector(6 downto 0)
    );
     
end ent_main;
architecture arch_main of ent_main is
signal counter : integer range 0 to 255;
signal okey    : std_logic_vector(3 downto 0);
begin
  -- counter logic:
  process(clock2_50)
  begin  
    if (clock2_50'event and clock2_50='1') then
        if (reset_n='0') then   -- reset button pressed ?
            counter   <= 0;      -- reset counter
            okey      <= "0000"; -- helper value to rememer previous state of buttons
        else
            if (key(0)='0' and okey(0)='1') then -- this cycle button pressed and previous cycle not pressed
                counter<=counter+1; -- increment counter
            elsif (key(1)='0' and okey(1)='1') then -- this cycle button pressed and previous cycle not pressed
                counter<=counter-1; -- increment counter
            else
                counter<=counter; -- keep counter value
            end if;    
            okey <= key; -- remember previous value of counter
        end if;
    end if;
  end process;
    
  -- display hex value on 7-seg 
  -- display bits 0 to 3 on first part of 7seg
  led0: entity work.ent_led7seg(arch_led7seg)
        port map(data=>std_logic_vector(to_unsigned(counter,8))(3 downto 0),leds=>hex0);
  -- display bits 7 to 4 on first part of 7seg
  led1: entity work.ent_led7seg(arch_led7seg)
        port map(data=>std_logic_vector(to_unsigned(counter,8))(7 downto 4),leds=>hex1);
  
 end arch_main;

and


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent_led7seg is
   port(data: in std_logic_vector(3 downto 0);
         leds : out std_logic_vector(6 downto 0)
       );
end ent_led7seg;
architecture arch_led7seg of ent_led7seg is
begin
    with data select
        leds<="1000000" when "0000",
              "1111001" when "0001",
              "0100100" when "0010",
              "0110000" when "0011",
              "0011001" when "0100",
              "0010010" when "0101",
              "0000010" when "0110",
              "1111000" when "0111",
              "0000000" when "1000",
              "0010000" when "1001",
              "0001000" when "1010",
              "0000011" when "1011",
              "1000110" when "1100",
              "0100001" when "1101",
              "0000110" when "1110",
              "0001110" when "1111",
              "0001000" when others;
  
end arch_led7seg;

Best Regards,

Johi.

Altera_Forum · ‎01-24-2017

Does this two codes work together?

And also if i only want from 0-15 do i have to change the integer from 0-255 to 0-15

Altera_Forum · ‎01-24-2017

Hello Malvin,

The second file is a module used in the first file.

I think i went much further than i normally go to show you a path to find an answer to your question.

I suggest you try to experiment a bit, make some changes and see where you get.

Good luck,

Johi.

Altera_Forum · ‎01-24-2017

I just re-read your question and noticed you want to write an altera program. You should look into the differences between hardware (everything gets done at the same time) and software (everything gets done sequentially, disregarding multithreading).

Altera_Forum · ‎01-28-2017

Check out this online training. It will give you lots of the basic info you need to write an HDL. As mentioned you have to think in terms of hardware instead of software.

https://www.altera.com/support/training/course.html?coursecode=ohdl1110