use OVL (Open Verification Library) with Quartus II VHDL

[Altera_Forum]

Hi hi!! 

I'm trying to add some assertions to my VHDL design (ex. ovl_always). I got the library from accellera (V2.6), and I just don't know which files should I ADD (Assignments/files/) to my project or can I just add the library at Assignments/libraries/project libraries? And how am I supposed to include the library in my source  library ???? or  use ??.??.all regards  murillo   ps: the assertion looks like this error_1: ovl_always generic map(OVL_ERROR, OVL_ASSERT, "Error: Data_LH high", OVL_COVER_NONE, OVL_POSEDGE, OVL_ACTIVE_LOW, OVL_GATE_CLOCK) port map (clk, rst_n, '1', data_lh, open);

[Altera_Forum]

OVL entities are meant for simulation, not for synthesis, so shouldnt be included in a quartus project.

[Altera_Forum]

Thanks Tricky, i know they are used for simulation and verification but i want to have them together with my code! 10 vhdl checkers in the OVL are synthesizable check page 12 (Accellera Standard OVL V2, Library reference manual Dec 2011) This doc its packed together with the library at docs! https://www.alteraforum.com/forum/attachment.php?attachmentid=6318  

regards m

[Altera_Forum]

You need to include the source files in your project. Quartus is pretty rubbish at library management so just keep with what you would usually write for modelsim, and quartus will just search all source files in the project for the relavent entity (it basically just ignores the library name you put - it almost treats every library as if it were the work library).

[Altera_Forum]

So guys/girls!! It was not so easy, but it works! 

Step by Step:  1. Write a ovl_always checker in your VHDL source file, Add also at the header   use work.std_ovl.all;  use work.std_ovl_components.all;  2. Add to your Quartus project (Assignments/Settings/Files/) the next files from the OVL library  std_ovl/std_ovl.vhd  std_ovl/std_ovl_components.vhd  std_ovl/vhdl93/syn_src/std_ovl_procs_syn.vhd  std_ovl/std_ovl_clock_gating.vhd  std_ovl/std_ovl_reset_gating.vhd  std_ovl/ovl_always.vhd  std_ovl/vhdl93/syn_src/ovl_always_rtl.vhd  3. You have to edit the ../std_ovl/vhdl93/syn_src/std_ovl_procs_syn.vhd and change all "default" with another constant name, for example "const_default" If you dont change it, quartus will come up with an error, because default is a reserved keyword ( i think its a verilog 95 reserved keyword!!!) Error (10500): VHDL syntax error at std_ovl_procs_syn.vhd(227) near text "default"; expecting "(", or an identifier ("default" is a reserved keyword), or unary operator  4. Edit also the ../std_ovl/std_ovl.vhd  on line 162 change  constant OVL_MSG_NUL : string(10 to ovl_msg_default_type'high) := (others => NUL); to  constant OVL_MSG_NUL : string(10 to ovl_msg_default_type'high) := (others => '0'); if not youll get a  Error (10606): VHDL Aggregate error at my_src.vhd(275): record aggregate must assign values to every element of record type ovl_ctrl_record  5. Thats it!!!  6. Now you can copy the constant OVL_CTRL_DEFAULTS (type ovl_ctrl_record) from std_ovl.vhd to your main source package and from there you can control "ALL" your checkers in your design!!! dont forget in your main package the: use work.std_ovl.all;  7. You can also have the checkers synthesised in hardware. For ex. The ovl_always checker have 4 inputs and one output. The inputs are clock, reset, enable and "the expresion to test" and the output fire[2 downto 0]. If enable is fixed '0'-low or fire is not connected, the checker will not be synthesised in hardware. But if you connect enable and fire, you can have your checkers in hardware and you can check asserts and coverage with the fire output (in hardware)!!!!  tip: you can also include olv_never. Both checkers are very useful to get started with assertions.. checkers!!!  see you girls/guys... hope it helps someone out there!! Gruß, m  using : Quartus II 64-bit Version 10.0 build 262 08/18/2010 SJ Full Version

[Altera_Forum]

vhdl 2008 has a new keyword default which is causing the problem. You could either do what you've done (Im never happy modifying library code like this) or change the code compile language to VHDL 1993.

[Altera_Forum]

Hey Hi! Thats a good tip!! Its just a pity I cant use 2008!!! 

Yeah I know is not the best workaround.. i also dont like it!:confused: I think they just didnt test it on all synth. tools!! Or maybe just in one! :) and it wasnt Quartus!

[Altera_Forum]

Its more to do with the fact the OVL libraries were probably written without thinking about VHDL 2008. In VHDL 1993 and 200X default was not a reserved keyword, hence you were free to use it in instance/signal/variable names. But in 2008 you cant (and hence the conflicts) 

 Have you tried compiling with VHDL 93?

[Altera_Forum]

Yes!! Tricky! It works with VHDL 1993!!! Well I think maybe Accellera is going to fix it (update it to VHDL2008) in the next version!! I hope so!!  

Thank's!!!