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using PFL in MAX II and MAX V

Altera_Forum
Honored Contributor II
‎04-22-2013 02:03 AM
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Hi, guys, recently, I am studying to use PFL in max cpld for FPP configuration of FPGA. I found that when I used PFL in max v 5m570zt100c5, the time requirement was not met (Fmax was less than 30mhz), while used in max ii epm570zt100c5, the time requirement was met( Fmax was higher than 50mhz). I think max v should be easier to meet the time requirement than max ii. Can anyone help figure out what's wrong? Thanks.

fpga_fpp.qar
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Altera_Forum
Honored Contributor II
‎06-10-2015 08:41 AM
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Check the speed grade. 

Example: MaxII speed grade 4 is not same as MAXV speed grade 4.
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