virtual clock - latch and launch clock on same cycle

[NitzanD]

Hi,

I am defining a virtual clock in .fdc file for work with external device as in the link here: 
https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/creating-virtual-clocks.html

When calculating setup timing - Quartus fails on paths from my system_clk to the virtual clock because it refers to it as if the launch and latch are on the same cycle (picture attached).

How can I change Quartus STA to set the launch and the latch clock to be in next cycle ?

Thanks ahead,
Nitzan

[sstrell]

Very difficult helping with this without seeing your .sdc.  Can you post it?

[NitzanD]

Do you mean .scf file ?
I synthesize with synplify_premier which uses Quartus for P&R, so I have .fdc file and .scf file  

[Nurina]

Hi Nitzan,

Can you share your .qar file? To generate this, go to Project>Archive Project.

Regards,

Nurina

[NitzanD]

where to upload it? 
I don't want to share it on the forum.


BR
Nitzan

[sstrell]

You don't have a .sdc file with your timing constraints in it? (create_clock, set_input_delay, etc.)

[Nurina]

Hi Nitzan,

You can share in email. I'm sending you an email shortly.

Regards,

Nurina

[NitzanD]

Hi, have you seen my email? I sent it as you asked. 

[Nurina]

Hi,

Yes I have. Can you please try set_multicycle_path as stated in the email? I have sent detailed information in email.

Regards,

Nurina

[NitzanD]

Hi,
In addition to what I sent in email, I want you to see again this picture that happens when I don't define 'multicycle path' :

Also another question - do the real clock and virtual clock should be in the same async group? 
set_clock_groups -asynchronous -group [get_clocks { main_clk main_clk_virt}]

BR
Nitzan

[SyafieqS]

Hi Nitzan,

It seems like you are encountering a setup timing violation issue in your design involving a virtual clock in a .fdc It is hard to see without the full constraint. I am suspecting there might be an issue on the input/output delay calculation that causing the launch and latch clock to be in the same phase.

Also another question - do the real clock and virtual clock should be in the same async group?

-From what I am seeing, in the scenario you've described with a real clock and a virtual clock, the concept of asynchronous clock domains might not directly apply. Both clocks are likely derived from the same master clock and are intended to be related, just with different clock frequencies or phases. Therefore, they may not need to be considered as separate asynchronous clock domains

[Nurina]

Hello Nitzan,

Usually you don't have to specify that real clock and virtual clock are in different clock groups.

As mentioned in email, I think the problem is that you are using the same virtual clock for both input and output delay.

Have you tried using different virtual clocks for input and output delay?

Regards,

Nurina

[NitzanD]

I haven't. why should they be different ? 

BR
Nitzan

[Nurina]

Hi Nitzan,

We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Best regards,

Nurina W.

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