voltage level of GPIO pins of Cyclone 10 GX

[Altera_Forum]

Hi all, 

 I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA has just 48 pins (1 i/o ) bank that supports I/O standards upto 3.3 V ,rest all pins among the other 280+ pins are supporting standards only upto 1.8 v .  One of the 3.3V peripherals itself have around 60-70 I/O pins , using a voltage translator chips might introduce skew between the signals...as voltage translator chips generally only support max upto 32 signals.  If anyone can suggest a workaround to effectively use Cyclone 10 GX smoothly.  Thanks, fpga993

[Altera_Forum]

How about using a second FPGA or CPLD as a voltage translator?

[Altera_Forum]

Thank you for the answer...I guess that's the only solution... Could you name some FPGA families that would suffice...so that there is a tradeoff between cost and complexity..as the second FPGA only has to handle the voltage translation...a lower cost FPGA would be enough I assume?

[Altera_Forum]

I'd look at the MAX10 family. Cheap, a range of small packages and doesn't require an external configuration device (FLASH).

[Altera_Forum]

Hey grateful for the replies!! 

 Even I was contemplating to either come down to either MAX II or MAX 10.Now MAX 10 looks a better option .  I also wanted to clear one more doubt.As I have already told my PCI peripheral uses around 70 signals and keeping voltage translator might introduce skew among the signals....why not go for an option of synchronizers in fpga? Is the implementation of synchronizer in fpga feasible?

[Altera_Forum]

What exactly do you mean by "synchronizer". If you want to control the skew in your signals you can specify what you need through the timing constraints for the MAX10. You can guarantee the max skew this way.