Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
The Intel sign-in experience is changing in February to support enhanced security controls. If you sign in, click here for more information.
19700 Discussions

what is meant by reset bridge

skuma161
Beginner
532 Views
 
0 Kudos
1 Reply
sstrell
Honored Contributor III
112 Views

Assuming you are referring to Platform Designer, the reset bridge component allows you to distribute a reset signal from outside a system to all the components inside the system. It has a reset sink interface on one side and a reset source interface on the other. The sink is typically exported to connect to an outside reset signal, while the source is connected to the reset inputs of all the other components in the system. You can learn more about the reset bridge and other basic components here:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer...

 

#iwork4intel

Reply