We need supply the ref clk for 1G/10G multi rate ethernet phy ipcore
we want to know what is the ref clk requirement of 322M CDR_Ref clk and 125M CDR_Ref clk
Can you elaborate further on what you mean by CDR refclk requirement ?
Typically we would expect user to provide free running, stable clock with the correct frequency using IO standard set in Quartus design.
This would be all the design requirement for CDR refclk.