what's non-inverted input pin ?

[Altera_Forum]

Hello,  

During complete my project, I stuck at a problem with pll. I use kit Cyclone III devlopment kit I try to use clock 50MHz to feed pll1 by pin AH15. During synthesing and analyzing it returns error:   Error (15065): Clock input port inclk[0] of PLL "adc_pre:inst1|CLOCK_GEN:clkinst|altpll:altpll_component|CLOCK_GEN_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block  Info (15024): Input port INCLK[0] of node "adc_pre:inst1|CLOCK_GEN:clkinst|altpll:altpll_component|CLOCK_GEN_altpll:auto_generated|pll1" is not connected  Also, I found a solution here. but it doesn't help me. I try to write the code to the .qsf file in folder of quartus project. But it doesn't help.  http://www.altera.com/support/kdb/solutions/rd02012010_744.html  What does the " non-inverted input pin" mean? and How can I resolve this problem? Please help me, thanks

[Altera_Forum]

It means that the PLL needs to be driven from a pin with a CLKIN or DIFFCLKIN_P function, but not a DIFFCLKIN_N (inverted input) function (unless your clock is a differential input, in which case, both DIFFCLKIN_P and N would be used). 

 Cheers, Dave

[Altera_Forum]

--- Quote Start ---  It means that the PLL needs to be driven from a pin with a CLKIN or DIFFCLKIN_P function, but not a DIFFCLKIN_N (inverted input) function (unless your clock is a differential input, in which case, both DIFFCLKIN_P and N would be used).  Cheers, Dave  --- Quote End ---   Hi Dave, I connecti it to pin AH15, which is oscilator 50Mhz, so is that DIFCLKIN_N or any kind of inverted signal?  And why does and how can Quartus seperate two kind of clocks when they are only about 180 o different phase. Sorry if the questions just like stupid, I don't study any course of FPGA, I study by myself. Thanks,

[Altera_Forum]

--- Quote Start ---   I connect it to pin AH15, which is oscilator 50Mhz, so is that DIFCLKIN_N or any kind of inverted signal?    --- Quote End ---   I cannot tell you without knowing the exact part number of the FPGA. Post a link to the "Cyclone III development kit" you are using and I'll look.    --- Quote Start ---   And why does and how can Quartus seperate two kind of clocks when they are only about 180 o different phase. Sorry if the questions just like stupid, I don't study any course of FPGA, I study by myself. Thanks,  --- Quote End ---    I'm not sure what you are asking here. If the signal is defined as differential, then the FPGA will use a differential receiver to receive the clock. If however the clock is defined as single-ended, then the FPGA will use a single-ended buffer. In that case, the single-ended signal may be restricted to enter the device on the DIFFCLKIN_P pin. I don't recall whether this is always the case. Typically I synthesize a design using Quartus to confirm clock assignments. The details on which clock pins route to what PLLs can also be found in the handbook for the device you are using.  Start by posting a link to the kit, and I'll point you to the appropriate place in the Cyclone III handbook where it provides the information.  Cheers, Dave

[Altera_Forum]

I suppose it's the cIII120 design kit, which connects clkin50 to CLK12 (AH15) I don't exactly understand the error. CLK12 should work as PLL input.

[Altera_Forum]

THe clock distribution, the clock input pins, the diff- clock output and the PLL connection has dedicated claim, please look the altera datasheet.

[Altera_Forum]

--- Quote Start ---  I cannot tell you without knowing the exact part number of the FPGA. Post a link to the "Cyclone III development kit" you are using and I'll look.    I'm not sure what you are asking here. If the signal is defined as differential, then the FPGA will use a differential receiver to receive the clock. If however the clock is defined as single-ended, then the FPGA will use a single-ended buffer. In that case, the single-ended signal may be restricted to enter the device on the DIFFCLKIN_P pin. I don't recall whether this is always the case. Typically I synthesize a design using Quartus to confirm clock assignments. The details on which clock pins route to what PLLs can also be found in the handbook for the device you are using.  Start by posting a link to the kit, and I'll point you to the appropriate place in the Cyclone III handbook where it provides the information.  Cheers, Dave  --- Quote End ---    My kit is "cyclone III 3c120 dev" Here is its link: http://www.altera.com/products/devkits/altera/kit-emb-dev-cyc3.html

[Altera_Forum]

Yes, At previous design, I used pin AH15 for ppl1 and it did well.  

Have you see the link I posted: "http://www.altera.com/support/kdb/solutions/rd02012010_744.html". This link tells about this error but I don't understand so much.

[Altera_Forum]

--- Quote Start ---  My kit is "cyclone III 3c120 dev" Here is its link: http://www.altera.com/products/devkits/altera/kit-emb-dev-cyc3.html  --- Quote End ---    I've uploaded a simple blink-LEDs design. The design uses AH15 as the input clock and a PLL.   If you open the pin planner GUI (Assignments->Pin Planner) and zoom in on pins, it will show you the pin functions, eg., see the attached pin_planner.jpg which shows AH15 is DIFFCLK_7n/CLK12.  I had no problem assigning this pin using Quartus 11.1sp1. Could you please try building this example design - just open the design in Quartus and press the play button.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Have you see the link I posted: "http://www.altera.com/support/kdb/solutions/rd02012010_744.html". This link tells about this error but I don't understand so much.  --- Quote End ---   The link is about a problem related to formal verification rather than regular design implementation. As Dave told, the clock pin can be used as single ended clock input without restrictions. Either you have made additional settings not mentioned in your post, or you are facing a specfic Quartus bug.

[Altera_Forum]

Ok, thankyou Dave, FvM, Adrianer!  

Finally I find out the problem.  I use block schemata to connect inputs, outputs to clock of pll, but I don't use wire, I put the clock input beside (adjecent) to the clock pin of block pll. For normal pin it connects automatically, but in this case it doesn't connect to clock of pll. Then I put the clk input a distance from block pll and wire them by wire. It works. It took me 2 days!!!

[Altera_Forum]

I'm glad to hear you figured out your problem. Thanks for posting your solution. 

 Cheers, Dave