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How are physical cores arranged in a mesh interconnect ?

How are physical cores arranged in a mesh interconnect. Are they arranged column wise, row wise or any other order.

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Employee
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Re: How are physical cores arranged in a mesh interconnect ?

Hello 3000023049911.5671101519166558E12,

 

Thank you for posting on the Intel ® communities.

 

I would like to know specifically of what processor are we talking about, this information is necessary so I can provide you with an accurate response.

 

Let me know please.

 

 

David V

 

Intel Customer Support Technician

A Contingent Worker at Intel

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Re: How are physical cores arranged in a mesh interconnect ?

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Re: How are physical cores arranged in a mesh interconnect ?

Help to understand I can't find the answer whether my processor supports Virtualization technology ? Gold G5400 Processor ...

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Employee
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Re: How are physical cores arranged in a mesh interconnect ?

Hello 3000023049911.5671101519166558E12,

 

Thank you for your response.

 

I will forward the information to the appropriate department for support. 

 

Hello DDRUG,

 

I would recommend you create a new support forum for assistance with your inquiry, keep in mind that the original topic is related to a completely different product.

 

 

Regards,

David V

 

Intel Customer Support Technician

Under Contract to Intel Corporation

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Re: How are physical cores arranged in a mesh interconnect ?

Hello,

 

Thank you for contacting Intel Xeon Community.

 

I was reviewing this thread and I noticed you are wondering about the architecture of the physical cores for the Intel Xeon Gold 5120 Processor. In the Intel Xeon Scalable platform, Intel Mesh Architecture with up to 28 cores, the Last Level Cache (LLC), six memory channels and 48 PCIe* channels are shared among all the cores.

 

On the previous number of generations, Intel has been adding cores onto the die and connecting them via a ring architecture. This was sufficient until recently. With each generation, the added cores increased the access latency while lowering the available bandwidth per core. Intel mitigated this problem by splitting up the die into two halves each on its own ring. This reduced hopping distance and added additional bandwidth but it did not solve the growing fundamental inefficiencies of the ring architecture.

 

This was completely addressed with the new mesh architecture that is implemented in the Skylake server processors. The mesh consists of a 2-dimensional array of half rings going in the vertical and horizontal directions which allow communication to take the shortest path to the correct node. The new mesh architecture implements a modular design for the routing resources in order to remove the various bottlenecks. That is, the mesh architecture now integrates the caching agent, the home agent, and the IO subsystem on the mesh interconnect distributed across all the cores. Each core now has its own associated LLC slice as well as the snooping filter and the Caching and Home Agent (CHA).

 

Additional nodes such as the two memory controllers, the Ultra Path Interconnect (UPI) nodes and PCIe are not independent nodes on the mesh as well and they now behave identically to any other node/core in the network. This means that in addition to the performance increase expected from core-to-core and core-to-memory latency, there should be a substantial increase in I/O performance. The CHA which is found on each of the LLC slices now maps addresses being accessed to the specific LLC bank, memory controller, or I/O subsystem. This provides the necessary information required for the routing to take place.

 

If you would like to check more details please go to the following third-party website it has pretty useful information:

 

https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server) / Section: Mesh Architecture.

 

Please check the file below, on page 3 you will have more information about the Mesh Architecture of this Intel Processor as well:

 

Datasheet:

https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-scalable-platform-b...

 

As additional information, I would like to share with you the Datasheet of the processor:

 

Intel® Xeon® Processor Scalable Family Datasheet:

https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-scalable-datasheet-vol-...

 

Please if you have more questions or need more information about it let me know and I will be more than happy to assist you.

 

Regards,

 

Emeth O.

Intel Customer Support Technician

Under Contract to Intel Corporation

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Re: How are physical cores arranged in a mesh interconnect ?

Hello,

 

I would like to know if you have any other questions in order to assist you.

If so, please do not hesitate and let me know and I will be more than happy to help you.

 

Regards,

 

Emeth O.

Intel Customer Support Technician

Under Contract to Intel Corporation

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Re: How are physical cores arranged in a mesh interconnect ?

Hello,

 

I am following up on this thread and I have not seen any activity recently.

 

Please if you have any other questions do not hesitate and contact us back and we will be more than happy to assist you.

 

Regards,

 

Emeth O,

Intel Customer Support Technician

A Contingent Worker at Intel

 

 

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