How access to I/O space is separated from access to memory space in PCI bus. Please explain by PCI signals and the protocol. How an Intel
CPU like Core 2 Due mobile separates I/O space from memory space? What electrical signals are involved in this process?
When accessing I/O space, is BE# [3::0] signals of PCI protocol(byte enables) are used in PCI protocol like memory access?
This community mostly does Server stuff. For chipset and processor questions, you may have better luck asking in one of those communities, if you don't get much response here.