Intel MBA, PMC

[GioFari]

Hello everyone,

I have some questions:

- Why the Intel not support interrupt signaling with MBM e CMT, but just explicit sampling?  

- how could I count more performance monitoring events with only one PMC? I saw that legacy architecture had cascade counters, and now?? Furthermore for this purpose I thought to use PEBS, but PEBS not support all events.

[SergioS_Intel]

Hello GioFari,

Thank you for contacting Intel Customer Support.

Can you please provide us the model of the Intel(R) product that you are referring to? This will help us to properly assist you.

Best regards,

Sergio S.

Intel Technical Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios

[GioFari]

The micro-architecture is  a Cascade Lake. 

[SergioS_Intel]

Hello GioFari,

Thank you for the information, can you please let us know the specific if this is about a processor or a chipset? If so can you please provide the exact model?

We will be looking forward to your updates.

Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios

[GioFari]

Xeon scalable 2nd generation Gold

[SergioS_Intel]

Hello GioFari,

Thank you for the missing information, please allow us to check your previous questions and we will get back to you.

Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios

[SergioS_Intel]

Hello GioFari,

Thank you for waiting for our updates.

We have a community that can assist him with these questions.

https://community.intel.com/t5/Software-Tuning-Performance/bd-p/software-tuning-perf-optimization

Additionally, you can find more information here:

https://software.intel.com/content/www/us/en/develop/articles/introduction-to-memory-bandwidth-allocation.html

https://www.intel.com/content/www/us/en/architecture-and-technology/resource-director-technology.html

https://software.intel.com/content/www/us/en/develop/topics/data-center.html

Finally, can you please let us know if you are a developer?

Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios

[GioFari]

I am a thesis researcher and I need some info. I know that MBM captures the memory bandwidth consumed by an RMID. However how it assigns the budget of writes operations to RMID ? The policy follows “The Last Modifier before the eviction of block?”

Thanks a lot,
Giorgio Farina

[SergioS_Intel]

Hello GioFari,

Thank you for the information, please allow us to check your previous questions and we will get back to you.

Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios

[SergioS_Intel · Accepted solution]

Hello GioFari,

Thank you for waiting for our updates, unfortunately the information that you are requesting is not available publicly.

We can only share information that is publicly available on our public Intel website.

All under information is confidential.

We do recommend posting your inquiry to the Intel community for possible peer-to-peer support: 

https://community.intel.com/t5/Software-Tuning-Performance/bd-p/software-tuning-perf-optimization 

We hope you find this information useful.

Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios