Table 5-41. DDR4 Command and Address Routing Guidelines, Memory Down

[Raj_Kr]

Hi,

I am using Intel Xeon Processor D-1746 in my design.

In the "576513_Idaville_LCC_PDG_Rev2_2" reference document, Routing & Length matching guidelines of memory down DDR4 are given.

Note: - Refer to the "Table 5-41. DDR4 Command and Address Routing Guidelines, Memory Down". In this table it is stated that "commands & address lines, from CPU pin to first DRAM Device length" should be greater than or equal to 2 inches trace length. It is correct? are we getting it write? do we really need to make sure that that all commands & address lines trace length should be greater than or equal to 2 inches?

If it is so then how this length to be measured for dual rank configuration?. as both ranks are routed in clamshell manner.

Thank You

Raj Kumar

[Mike_Intel]

Hello Raj_Kr,

Thank you for posting in Intel community Forum.

Base on your inquiry, we have specific forum for these issues or inquiries. I will be transferring this thread for faster response. 

If you have questions, please let us know. Thank you.

Best regards,

Michael L.

Intel Customer Support Technician

[Poojitha]

Hi Raj,

we recommend you to posting your query in the Embedded Community Forum to receive a quicker response regarding

https://community.intel.com/t5/Embedded-Products/ct-p/embedded-products

Embedded Products

Support for Intel® embedded products

 Regards,

Poojitha