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prefetch disable via MSRs on Nehalem?

idata
Employee
‎09-30-2009 04:47 AM
2,040 Views

Hi,

For the Core 2 Architecture ther had been the bits 9 and 19 on msr 0x1a0 which could be set to disable the hardware and the adjacent cache line prefetcher. This feature is described in the "Software Developer's Manual Volume 3B: System Programming Guide, Part 2" pp B46-B47.

For Nehalem/Core i7 this functionality is not documented. Is this information confidential and only part of a "BIOS Developer Guide"?

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Daniel_O_Intel
Employee
‎10-01-2009 10:36 AM
586 Views

Interesting question, but I've no idea how to answer it. Have you tried asking in the processor community? http://communities.intel.com/community/tech/processors might be able to help better.

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idata
Employee
‎10-01-2009 09:48 PM
585 Views
In response to Daniel_O_Intel

Thanks for the reply, I opened a new thread there. For all people looking for the same, the link is:

/thread/7096 http://communities.intel.com/thread/7096

(Hopefully there'll be an answer )

In response to Daniel_O_Intel
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