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idata
Community Manager
1,517 Views

prefetch disable via MSRs on Nehalem?

Hi,

For the Core 2 Architecture ther had been the bits 9 and 19 on msr 0x1a0 which could be set to disable the hardware and the adjacent cache line prefetcher. This feature is described in the "Software Developer's Manual Volume 3B: System Programming Guide, Part 2" pp B46-B47.

For Nehalem/Core i7 this functionality is not documented. Is this information confidential and only part of a "BIOS Developer Guide"?

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2 Replies
Daniel_O_Intel
Employee
63 Views

Interesting question, but I've no idea how to answer it. Have you tried asking in the processor community? http://communities.intel.com/community/tech/processors might be able to help better.

idata
Community Manager
63 Views

Thanks for the reply, I opened a new thread there. For all people looking for the same, the link is:

/thread/7096 http://communities.intel.com/thread/7096

(Hopefully there'll be an answer )

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