Reading the "Knights Corner Instruction Set Reference Manual" I see that there are 32 vector registers where the x64 instruction set has only 16. The V register field and the R register field in the MVEX prefix are extended with an extra bit (V', R') to code the extra registers. But the B and X fields are not extended. How do you code register zmm16 - zmm31 in an instruction with three or more register operands? Is this impossible, or are you using some other bits, like the pp bits which are mostly unused anyway or the unused bit to the left of the pp bits? Maybe you are using the X bit, which is not needed anyway if there is no memory operand, to extend the B bits. Then the only limitation would be that registers zmm16 - zmm31 cannot be used with VSIB addressing. Are the extra bits inverted?
I would like to update my disassembler (named "objconv") to cover this instruction set so I need this info.
Thank you for catching these doc issues. I don't have hardware to test but I believe
1. in VSIB encoding, the index operand would be encoded with MVEX.V'X
2.There was a latent notation change that led to two different notation expressing the same feature. MVEX.aaa is the correct notation that replaces MVEX.kkk.
3. I believe the notation convention of transform_modifieris consistent with the table listed in pg 47
4. It turns out, the mmmm=0000 mapwas used to encode some of the scalar mask instructions.
With upated correction.
I think it suffices to infer from the CPUID section of this doc that the instruction set support (addition/subtraction) in Knights Corner that are not covered by feature flags is captured by the Family/model.
The 32-bit mode question is treading into tech support scope outside of my interest. I should leave that for more qualified folks.