KNL MCDRAM frequency

[Daejin_J_]

Hello,

Does anyone know how to adjust MCDRAM frequency on KNL?

I have confirmed that the DDR channel frequency can be controlled by the BIOS, but I don't know how to control that of the MCDRAM.

Do you think that it is possible to adjust MCDRAM frequency from MSR or CSR register etc.?

I desperately want to decrease MCDRAM frequency to half the level.

Is there any idea?

Thank you,

Daejin.

[McCalpinJohn]

The frequency of the interface between the MCDRAM and the mesh can be easily computed using the ECLK performance counter in the KNL uncore.

I have not seen any indication that there are options to modify the value.

[SergeyKostrov]

>>...I desperately want to decrease MCDRAM frequency to half the level... My question: Is there any technical issue / problem with MCDRAM in you application?

[Gregg_S_Intel]

I think MCDRAM frequency is tied to the uncore frequency.  I don't recall whether control of uncore frequency was included in the BIOS.

[Daejin_J_]

McCalpin, John wrote:

The frequency of the interface between the MCDRAM and the mesh can be easily computed using the ECLK performance counter in the KNL uncore.

I have not seen any indication that there are options to modify the value.

Dear McCalpin, John, @

could you access to the following documents below?

1. Knights Landing Processor - External Design Specification (EDS) - Volume Two: Registers, Part A, Doc ID # 546888

2. Knights Landing Processor - External Design Specification (EDS) - Volume Two: Registers, Part B, Doc ID # 552048​

The ECLK performance counter you mentioned does not seem to have registers to control MCDRAM frequency.

I think I need to check the EDS documentations, but I can not access.

Note that only the DDR frequency is adjustable in the BIOS, even though there is no indication in the UCLK  performance counter to modify DDR frequency.

Thank you.

[McCalpinJohn]

As with DDR memory, I think it is extremely unlikely that the MCDRAM frequency can be changed on a "live" system -- this can only be done by the BIOS before the system switches into a mode where it actually uses the memory.   Even if you could find a description of the bits that needed to be changed, you would have to modify the BIOS to perform that setup.  

There is also a pretty good chance that at least some part of the Processor to MCDRAM_logic to MCDRAM_DRAM path won't work at 1/2 speed.  There is no compelling reason to support low-frequency operation, and the history of recent DRAM interfaces is to support a relatively low range of frequencies. 

Finally, it is possible that even if the hardware *could* support half-speed operation *and* you had a modifiable version of the BIOS, it is not clear that the algorithms that the BIOS implements for training the interface would be able to cover operation so far out of specification.  Intel may or may not have even evaluated whether the BIOS training algorithms might work at half speed, and if they did evaluate it, it might take a fairly significant effort to find the information, and would likely be impossible to get Intel to share it.

[SergeyKostrov]

>>...that only the DDR frequency is adjustable in the BIOS, even though there is no indication in the UCLK performance counter to modify >>DDR frequency... Are you looking for something similar to described at: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/9700-series-brief.pdf and on page 2 take a look at "Memory Dynamic Clock Enable support".