Software Tuning, Performance Optimization & Platform Monitoring
Discussion around monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform monitoring
Announcements
This community is designed for sharing of public information. Please do not share Intel or third-party confidential information here.

About PMU

Kelvin_C_
Beginner
178 Views

I'm new to PMU development, I'm curious about the following question about PMU:

1) I have read IA32_MISC_ENABLE MSR and the bit[7] always is zero , but the bit[12] always set, what does it mean? The CPU is supported PEBS or not supported??

2) Does PEBS provided the functionality that can trap all of branch , such as , syscall ? what is the basic step for doing this?

3) without PEBS , I tired to set a PMC0 with Ia32PerfEvtseL0 , and set the PMC0 to be negative number ,  however, the PMI doesn't happened... why is that..??

4) I have do a following setting , but there is not PMI generated

{AA2A6F71-E766-4504-BCF3-B64F0857760A}.png

CPU Model : 60 

where g_Event is 0xC2 and g_mask is 1 

 

Thank you :)

0 Kudos
0 Replies
Reply