The question might sound strange as SDM explicitly says that those events are not available on SNB. But some posts on forum assume that they are So I could make a conclusion it is only matter of documentation.
The events are not in the SDM sandybridge event table 19-8.
Sometimes when an event is not in the SDM it is because the event doesn't count correctly. It may give a non-zero count on SNB but you should take the counts with a grain a salt.
If I were using the event, I'd probably run a sanity check on the event with a memory latency check and a memory bandwidth test. And maybe check that, say, CYCLE_ACTIVITY.CYCLES_LDM_PENDING gives near zero count when you run a latency or bw test for sizes which fit into L2 (or L3 if your processor has one).
I don't see an event named CYCLE_ACTIVITY.STALLS_LDM_PENDING in the SDM.
These events are also not defined in the VTune database files for the Sandy Bridge platforms (but are defined for the Ivy Bridge and Haswell products). This also suggests that the event is either unimplemented or unreliable.
The other forum thread referred to above lists 7 sub-events to CYCLE_ACTIVITY (0xA3):
0xA3 0x01 CYCLE_ACTIVITY.CYCLES_L2_PENDING
0xA3 0x08 CYCLE_ACTIVITY.CYCLES_L1D_PENDING
0xA3 0x02 CYCLE_ACTIVITY.CYCLES_LDM_PENDING
0xA3 0x04 CYCLE_ACTIVITY.CYCLES_NO_EXECUTE
0xA3 0x05 CYCLE_ACTIVITY.STALLS_L2_PENDING
0xA3 0x06 CYCLE_ACTIVITY.STALLS_LDM_PENDING
0xA3 0x0C CYCLE_ACTIVITY.STALLS_L1D_PENDING
Of these events, only Umasks 0x01, 0x02, 0x04 are listed for Sandy Bridge EP in the SDM, but the implied combination Umaks of 0x05 and 0x06 are defined in the VTune database of events for the Sandy Bridge platforms. Events 0x08 and 0x0C are not included in the VTune database files for Sandy Bridge, but all 7 events are included in the VTune database files for Ivy Bridge and Haswell platforms.