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SamG
Beginner
301 Views

Calculating Uncore power consumption for sandybridge processors

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Hi,

I am currently using sandybridge servers with E5-2670 chips. RAPL is being used for power measurements.

The 3 domains provided are Package, Core and DRAM.

My understanding is:

Package - provides total power consumption of the processor package

Core - provides power consumption of the CPU cores only.

DRAM - Provides power consumed by the DRAM DIMMs (and is to be added with the package power for cases where I am interested in power consumed by the processor and DRAM)

Please correct me if there is any discrepancy in the above understanding. Also, how do I calculate the power consumed by the uncore part?

Will it be the same as [pkg power- core power]?

-Thanks in advance

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McCalpinJohn
Black Belt
301 Views

It does not seem like Intel wants to go into great detail in describing the RAPL interfaces -- they are intended to be good enough for power control, not necessarily good enough for laboratory measurements. 

In the case of Xeon E5 v1 (Sandy Bridge EP) processors, I have also made the assumption that the uncore energy consumption is contained in difference between the Package and PP0 energy consumption values.  It is challenging to validate the PP0 counters, since Sandy Bridge EP does not support independent control of core and uncore frequencies.   When I did testing on this (some years ago), I saw that benchmarks with higher uncore activity (e.g., streaming data from L3, versus cache-contained spinning) did have larger difference between PP0 and PKG energy consumption, but I could not think of any way to approach this at finer scales.

The PP0 domain has been dropped from Xeon E5 v3 and newer processors, so there is not a lot of incentive to go back and look at this.

Some validation work on the Sandy Bridge EP RAPL measurements is reported at https://doi.org/10.1109/ISPASS.2013.6557170

It looks like Xeon E5 v3 (Haswell) and newer processors use power measurements to produce the PKG RAPL energy numbers, rather than using an activity-based model (as was used in Sandy Bridge EP).  This makes the numbers more reliable (since no activity-based model can be correctly tuned for all possible workloads and all possible silicon characteristics), but without separate values for PP0.  Xeon E5 v3 and newer processors do have the ability to separately control core and uncore frequencies, so directed testing could be used to build models of how the energy consumption is distributed among the various units on the chip.

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3 Replies
McCalpinJohn
Black Belt
302 Views

It does not seem like Intel wants to go into great detail in describing the RAPL interfaces -- they are intended to be good enough for power control, not necessarily good enough for laboratory measurements. 

In the case of Xeon E5 v1 (Sandy Bridge EP) processors, I have also made the assumption that the uncore energy consumption is contained in difference between the Package and PP0 energy consumption values.  It is challenging to validate the PP0 counters, since Sandy Bridge EP does not support independent control of core and uncore frequencies.   When I did testing on this (some years ago), I saw that benchmarks with higher uncore activity (e.g., streaming data from L3, versus cache-contained spinning) did have larger difference between PP0 and PKG energy consumption, but I could not think of any way to approach this at finer scales.

The PP0 domain has been dropped from Xeon E5 v3 and newer processors, so there is not a lot of incentive to go back and look at this.

Some validation work on the Sandy Bridge EP RAPL measurements is reported at https://doi.org/10.1109/ISPASS.2013.6557170

It looks like Xeon E5 v3 (Haswell) and newer processors use power measurements to produce the PKG RAPL energy numbers, rather than using an activity-based model (as was used in Sandy Bridge EP).  This makes the numbers more reliable (since no activity-based model can be correctly tuned for all possible workloads and all possible silicon characteristics), but without separate values for PP0.  Xeon E5 v3 and newer processors do have the ability to separately control core and uncore frequencies, so directed testing could be used to build models of how the energy consumption is distributed among the various units on the chip.

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SamG
Beginner
301 Views

But by any chance, the package domain power does not include the DRAM power right?

McCalpinJohn
Black Belt
301 Views

The package domain definitely does not include the DRAM power on Sandy Bridge.

On later processors that use current-measurement-based energy computations, it is possible that a tiny amount of power consumed in the package DRAM drivers (which run at the same voltage as the DRAMs) could be included in the "DRAM" power domain.  This may vary by platform, depending on exactly how the board configures the voltage regulators that supply the voltage rails for the DRAMs and for the memory interface of the processor. 

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