Can clwb/clflush/clflushopt invalidate cache line in other core?

[spearNeil]

In Intel 64 and IA-32 Architectures Software Developer's Manual, there are similar descriptions of clwb/clfluflush/clflushopt instructions, which is "Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the linear address specified with the memory operand". I want to know whether clwb/clflush/clflushopt instructions invalidate(write back to memory) cache line(L1 and/or L2 cache) in other cores. In other words, suppose that one core is executing clflush, another core also caches the same data (64 bytes, aligned with cache line), and the two cores modified different bytes, what will happen to the core without executing clfush? Or, can anyone tell me whether "the cache coherence domain" contains all L1/L2 cache in different cores? 

[McCalpinJohn]

In current processors, the "cache coherence domain" includes all of the L1/L2/L3 caches in all of the processors in the system.   (The disclaimer is added because all caches may not be in the same coherence domain in all future systems.)

These instructions are "global" -- the specified line is invalidated in all caches in the system (if "clean") or written back to memory (if "dirty").  

These instructions are "coherency-safe" -- they cannot cause the system to get a different answer than if they were not executed.

The example you provide is not possible for the "WriteBack" memory type -- only one core can have a writable (Exclusive or Modified) copy of the cache line at a time.  The hardware enforces serialization of the stores so that they become visible in some order.

With the "Write Combining" memory type (or when using streaming/nontemporal stores with the WriteBack memory type), it is possible for two or more cores to write to the same cache line at the same time.   The hardware will execute the stores in some order and flush the write combining buffers to memory in some order (neither controllable by the user) and the value in memory will be the one from the last of the write combining buffer updates to arrive at the memory controller.

[spearNeil]

Thanks for your reply,

Before this, I misunderstood the cache coherency protocol (MESI/MESIF) because I read something that tells me only when using the memory access instructions with the LOCK prefix does the cache coherency protocol make sense. So I have the question above.

Besides,  I have another question about clwb/clflush/clflushopt, Does clwb/clflush/clflushopt sequentially write data from cache line back to iMC? - Intel Communities

Could you please tell me if my idea is correct? Thank you very much.

Best regards.