DRAM_DATA_READS/DRAM_DATA_WRITES

[James_M_3]

Referencing https://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/515830 On my 2 socket Ivy Bridge system, running "setpci -s 0:0.0 0x48.l" returns all zeros. Examining /proc/iomem does not help, in that I'm not seeing what I would intuitively think is the memory controller. Question - How can I reliably determine what the BAR value is on a given system, so I can do as Dr. McCalpin outlines to get the counters for determining total memory throughput? As an aside, I curious to know why access to these "counters" is so different from how we typically get event counts (programming control registers and reading counters via MSR reads and MSR writes)? Appreciate the guidance Jim

[A_T_Intel]

The DRAM_DATA_READS/DRAM_DATA_WRITES counters are for the Haswell client/desktop/single-socket processors and are not present on the Haswell server, two socket processors.  

Below is a link for documentation of uncore performance counters for Xeon:

https://www-ssl.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-uncore-performance-monitoring.html

[James_M_3]

Thank you.

Referencing the original link:

https://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel

I cut-and paste the text below. There's nothing in that post that would lead one to conclude that the DRAM_DATA_READS and DRAM_DATA_WRITES counters are only available on Haswell single socket. In fact, one would reasonably conclude from the opening paragraph that these counters are available on Sandy Bridge and Ivy Bridge.

Thanks

Jim

[James_M_3]

Oooppsss....Forgot to include the text from the referenced web page.

---------------------------------------------------------------------------------------------------------------

Dear Software Tuning, Performance Optimization & Platform Monitoring community,

The recent and upcoming Intel® Core™ processors of 2nd,3rd and 4th generation (previously codenamed Sandy-Bridge, Ivy-Bridge and Haswell) expose model specific counters that allow for monitoring requests to DRAM.

---------------------------------------------------------------------------------------------------------------

[McCalpinJohn]

The web page that you are linking to is describing the memory controller performance monitoring on the single-socket "client" processors only.  The dual-socket server processors have a completely different uncore with completely different performance monitoring features.

For your Ivy Bridge system, the document you want is "Intel Xeon Processor E5 v2 and E7 v2 Product Families Uncore Performance Monitoring Reference Manual".  This is document number 329468, and it looks like the latest revision is 002, from February 2014. 

For the Xeon E5-26xx v2 (Ivy Bridge), you can ignore references to "MC1" (Memory Controller 1), which is only present on the Xeon E7.  For the Xeon E5, all four of the channels should be connected to MC0.   Everything you need for the memory controller counters is in Section 2.5 of that manual.