Decoding the DIMM geometry

[CyrIng]

Hello,

Querying the PCi MCHBAR(0x44) of chipset 945 series, I try to decode the geometry of DIMMs in terms of rows, columns, banks, ranks

Using my Linux kernel module code, I'm getting the number of channels(2), banks and ranks and major latencies; but that's not enough to compute the size of each DIMM and total memory.

( Hardware is made of two 512MB PC2-5300 CL5 SODIMM )

I don't find the specific bits to compute the number of populated slots, rows, and columns ?

CoreFreq(0:-1): Processor [ 06_0F] Architecture [Core2/Conroe/Merom] CPU [2/2]
C0DRA0=3	C0DRA2=0
C0DRB=10101010
C0DRC0=40000a06
C0DRC1=f40e1900	C0DRC2=e000000
C0DCLK=3
C0BNKARC=0
C0DRAMW=1
C1DRA0=3	C1DRA2=0
C1DRB=1010
C1DRC0=40000a06
C1DRC1=f40e1900	C1DRC2=e000000
C1DCLK=3
C1BNKARC=0
C1DRAMW=0

typedef union
{	// Offset Channel0: 120h
	unsigned int		value;
	struct {
		unsigned int
		DT				:  2-0,
		ReservedBits1	:  4-2,
		SMS				:  7-4,
		ReservedBits2	:  8-7,
		RMS				: 11-8,
		ReservedBits3	: 29-11,
		IC				: 30-29,
		ReservedBits4	: 32-30;
	};
} P945_MC_DRC0;

typedef union
{	// Offset Channel0: 200h
	unsigned int		value;
	struct {
		unsigned int
		DAMC			:  2-0,
		SCS				:  3-2,
		ReservedBits1	:  9-3,
		Channel_XOR		: 10-9,
		Cha_XOR_Random	: 11-10,
		ReservedBits2	: 14-11,
		ReservedBits3	: 16-14,
		SMS				: 19-16,
		IC				: 20-19,
		IC_SMS_Ctrl		: 21-20,
		EMRS			: 23-21,
		ReservedBits4	: 24-23,
		ReservedBits5	: 29-24,
		ReservedBits6	: 32-29;
	};
} P945_MC_DCC;

void Query_P945(void __iomem *mchmap)
{	// Source: Mobile Intel 945 Express Chipset Family
	unsigned short channelCount, cha;
	unsigned int DRA0 = 0, DRA2 = 0, DRC1 = 0, DRC2 = 0, DRB = 0,
			BNKARC = 0, DCLK = 0, DRAMW = 0;
	P945_MC_DRC0 DRC0;
	P945_MC_DCC DCC;

	DCC.value = readl(mchmap + 0x200);

	switch (DCC.DAMC) {
	case 0b00:
	case 0b11:
		channelCount = 1;
		break;
	case 0b01:
	case 0b10:
		channelCount = 2;
		break;
	}

	for (cha = 0; cha < channelCount; cha++) {
		DRAMW = readw(mchmap + 0x40c + 0x80 * cha);
		DRA0 = readb(mchmap + 0x108 + 0x80 * cha);
		if (cha == 0) {
			DRAMW &= 0b11111111;
			DRA2 = readb(mchmap + 0x109 + 0x80 * cha);
			DRB = readl(mchmap + 0x100);
		} else {
			DRAMW &= 0b1111;
			DRA2 = 0;
			DRB = readw(mchmap + 0x180);
		}
		DCLK = readb(mchmap + 0x10c + 0x80 * cha);
		BNKARC = readw(mchmap + 0x10e + 0x80 * cha);
		DRC0.value = readl(mchmap + 0x120 + 0x80 * cha);
		DRC1 = readl(mchmap + 0x124 + 0x80 * cha);
		DRC2 = readl(mchmap + 0x128 + 0x80 * cha);

		printk("C%uDRA0=%x\tC%uDRA2=%x\n", cha, DRA0, cha, DRA2);
		printk("C%uDRB=%x\n", cha, DRB);
		printk("C%uDRC0=%x\n",cha, DRC0.value);
		printk("C%uDRC1=%x\tC%uDRC2=%x\n",cha, DRC1, cha, DRC2);
		printk("C%uDCLK=%x\n", cha, DCLK);
		printk("C%uBNKARC=%x\n", cha, BNKARC);
		printk("C%uDRAMW=%x\n", cha, DRAMW);
	}
}

Documentation is the datasheet of the Intel 945 Express Chipset Family; June 2008; Document Number: 309219-006

Thanks for any help

CyrIng