Please look at the "Intel 64 and IA-32 Architectures Optimization Reference Manual", appendix C.
Section C.2 defines instruction latency and throughput:
Latency - The number of clock cycles that are required for the execution core to complete the execution of all of the ops that form an instruction.
Throughput - The number of clock cycles required to wait before the issue ports are free to accept the same instruction again. For many instructions, the throughput of an instruction can be significantly less than its latency.
Section C.3 lists the latency and throughput for each instruction.
Hopefully this is what you are looking for.