Software Tuning, Performance Optimization & Platform Monitoring
Discussion around monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform monitoring
Announcements
This community is designed for sharing of public information. Please do not share Intel or third-party confidential information here.
1622 Discussions

Documentation on clock cycles for various Sandy Bridge instructions?

christian_conveygmai
148 Views
I need to do some back-of-the-envelope math regarding the maximum pace at which a Sandy Bridge processor can execute various double-precision operations (multiply, SIMD multiply, various trig functions, etc.)
Anyone know where I can get documentation on that?
Thanks,
Christian
0 Kudos
1 Reply
Patrick_F_Intel1
Employee
148 Views
Hello Christian,
Please look at the "Intel 64 and IA-32 Architectures Optimization Reference Manual", appendix C.
Section C.2 defines instruction latency and throughput:

Latency - The number of clock cycles that are required for the execution core to complete the execution of all of the ops that form an instruction.

Throughput - The number of clock cycles required to wait before the issue ports are free to accept the same instruction again. For many instructions, the throughput of an instruction can be significantly less than its latency.

Section C.3 lists the latency and throughput for each instruction.
Hopefully this is what you are looking for.
Pat

Reply