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NStoj
Beginner
232 Views

FPGA sending Interrupts to CPU

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Hello everyone,

I need some help on connecting FPGA board to Intel CPU in terms of interrupts. I need to understand how to connect FPGA interrupts to APIC/LAPIC controller in order to trigger interrupt per CPU Core… Is there some Motherboard which can allow this or I need to create my own board to be able to do this?

Thank you for your time.

Br,

Nikola

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1 Solution
McCalpinJohn
Black Belt
232 Views

PCIe devices are required to support MSIs, and gen3 devices should support extended MSIs (MSI-X).  I have not programmed this part of a system myself, but it is described relatively clearly in Chapter 17 of the MindShare book "PCI Express Technology".  Amazingly, the PDF is available directly from MindShare at https://www.mindshare.com/files/ebooks/PCI%20Express%20Technology%203.0.pdf

Bridging from the descriptions to actual code is likely to require a bit of effort, but given the abundance of open source PCIe device driver software, it should be possible....

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McCalpinJohn
Black Belt
232 Views

If the FPGA is on a PCIe board, then you will want to use the PCIe interrupt generation mechanism(s).

A reference on these for Xilinx FPGAs is https://www.xilinx.com/Attachment/Xilinx_Answer_58495_PCIe_Interrupt_Debugging_Guide.pdf

A reference for Altera FPGAs is http://www.alterawiki.com/wiki/Handling_PCIe_Interrupts

I can't imagine that anyone would build a PCIe board that did not support the generation of interrupts, but it is possible that a board has limited support for some of the classes of interrupts.  So you won't need to build a board, but you may need to build your own interrupt handler to be installed in the OS kernel.   There is a lot of documentation on the interwebs about interrupt handlers for Linux -- the hardest part (after figuring out the terminology) is figuring out whether a piece of documentation is relevant to the kernel you are using.  The Linux kernel folks are not shy about changing kernel internals between major versions (e.g., there were major changes between 2.6.18 and 2.6.32 that caused me some grief).   So the tutorials are good for learning the concepts, but when you are ready to start writing code, I recommend downloading the full kernel source for your current kernel and finding a driver in that tree to use as your starting point.

NStoj
Beginner
232 Views

Hi John,

Thank you for your reply!

Yes, indeed FPGA will have PCIe communication with CPU. Just to understand, your suggestion is to use PCIe link to generate IRQs which are not related to PCIe protocol ? We need IRQs which are not related to PCIe protocol.... IRQs coming from FPGA are execution rates for different CPU Cores so they are completely not dependent on PCIe protocol. Can this be done via PCIe MSIs ?

Best Regards,

Nikola

 

McCalpinJohn
Black Belt
233 Views

PCIe devices are required to support MSIs, and gen3 devices should support extended MSIs (MSI-X).  I have not programmed this part of a system myself, but it is described relatively clearly in Chapter 17 of the MindShare book "PCI Express Technology".  Amazingly, the PDF is available directly from MindShare at https://www.mindshare.com/files/ebooks/PCI%20Express%20Technology%203.0.pdf

Bridging from the descriptions to actual code is likely to require a bit of effort, but given the abundance of open source PCIe device driver software, it should be possible....

View solution in original post

NStoj
Beginner
232 Views

Hi John,

Thank you for suggestions and PDF link!

MSI-X sounds promising for what we need...

Best Regards,

Nikola

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