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Beginner
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Non-Architectural Performance Events don't have a CMSK specified

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Hi, i'm checking non-architectural performance events in "Software Developer's manual" related to the Skylake architecture. Events that requires to set CMASK to value x have the comment "CMSKx", but 2 events have the comment "CMSK" without a x value specified. They're IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK  (event_num=9CH, umask=01H ) and UOPS_EXECUTED.STALL_CYCLES (event_num=B1H, umask=01H )

Is it a mistake in the documentation or am i forgetting something?

 

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Black Belt
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It is not particularly easy to find out who is currently responsible for the documentation of the performance counters.... :-(

It looks like Intel is putting their most up-to-date documentation for the performance counters on the 01.org website:  https://download.01.org/perfmon/

The Skylake material is in https://download.01.org/perfmon/SKL/ and the full set of core events is in https://download.01.org/perfmon/SKL/skylake_core_v30.json and https://download.01.org/perfmon/SKL/skylake_core_v30.tsv.   ; The json file is a bit easier to read, and it clearly shows the CounterMask value as "1" for both the IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK event and the UOPS_EXECUTED.STALL_CYCLES event.

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If I am reading the VTune configuration files correctly, the event IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK (Event 0xC9, Umask 0x01) sets the CMASK to 1 and sets the INV flag as well.   The full register value used by VTune would be 0x01d3019c.  Note that this sets the interrupt on overflow bit (bit 20), which you may or may not want in your application.

The other event UOPS_EXECUTED.STALL_CYCLES also sets CMASK to 1 and sets the INV bit.  This makes sense -- CMASK=1 says to increment if the base event increments one or more times (i.e., 1 or more uops executed), then INV switches this to only count when the base increment increments less than 1 time.  The full register value used by VTune would then be 0x01d301b1.  Again, this includes the interrupt on overflow bit, which you may or may not want.

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Beginner
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McCalpin, John wrote:

If I am reading the VTune configuration files correctly, the event IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK (Event 0xC9, Umask 0x01) sets the CMASK to 1 and sets the INV flag as well.   The full register value used by VTune would be 0x01d3019c.  Note that this sets the interrupt on overflow bit (bit 20), which you may or may not want in your application.

The other event UOPS_EXECUTED.STALL_CYCLES also sets CMASK to 1 and sets the INV bit.  This makes sense -- CMASK=1 says to increment if the base event increments one or more times (i.e., 1 or more uops executed), then INV switches this to only count when the base increment increments less than 1 time.  The full register value used by VTune would then be 0x01d301b1.  Again, this includes the interrupt on overflow bit, which you may or may not want.

Thank you John, so SDM's authors forgot to add 1 after CMSK. Yuo can check it in the attachment.

Is is possible to signal the mistake to someone?

 

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Black Belt
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It is not particularly easy to find out who is currently responsible for the documentation of the performance counters.... :-(

It looks like Intel is putting their most up-to-date documentation for the performance counters on the 01.org website:  https://download.01.org/perfmon/

The Skylake material is in https://download.01.org/perfmon/SKL/ and the full set of core events is in https://download.01.org/perfmon/SKL/skylake_core_v30.json and https://download.01.org/perfmon/SKL/skylake_core_v30.tsv.   ; The json file is a bit easier to read, and it clearly shows the CounterMask value as "1" for both the IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK event and the UOPS_EXECUTED.STALL_CYCLES event.

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Beginner
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Thank you, The linked tables are what i needed a couple of months ago. I made a CSV table of PMCs, but i had problems with the documentation.

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