Hello,
I've been looking into the number of slices a CHA handles, and I read on @McCalpinJohn 's research paper that _typically_ each slice is handled by one CHA.
However, there are cases like the "Knights Landing (KNL): 2nd Generation Intel® Xeon Phi™ Processor" where each 2 cores are connected to a CHA (I assume in that case each CHA handles 2 slices?).
So is it safe to assume that by reading the CAPID6 register's value and finding the number of active CHAs, we can later derive that `num_cores / num_CHAs` gives us the number of slices assigned to each CHA, hence `cha_num * slice_per_cha` would give us the total number of slices for the L3/LLC?
Are there any cases that contradict this assumption?
Thank you for your time in advance.
- Mani
